zhajio1988 / uvm_candy_loverLinks
UVM candy lover testbench which uses YASA as simulation script
☆17Updated 5 years ago
Alternatives and similar repositories for uvm_candy_lover
Users that are interested in uvm_candy_lover are comparing it to the libraries listed below
Sorting:
- soc integration script and integration smoke script☆24Updated 3 years ago
- This is the UVM environment for UART-APB IP core. This environment contains full UVM components. It is only used for studing and invetiga…☆24Updated 5 years ago
- ☆26Updated 4 years ago
- work in SSRL, SOC/NOC/Chiplet Design, DDR/UCIe/PCIe, UVM Framework☆35Updated 2 years ago
- ☆43Updated last year
- Verilog cache implementation of 4-way FIFO 16k Cache☆20Updated 12 years ago
- UVM register utility generation by inputting xls table☆39Updated 2 years ago
- uvm_axi4lite is a uvm package for modeling and verifying AXI4 Lite protocol☆28Updated 8 months ago
- UVM APB VIP, part of AMBA3&AMBA4 feature supported☆32Updated 5 years ago
- generate UVM testbench using python☆28Updated 7 years ago
- ☆12Updated 9 years ago
- DDR3 function verification environment in UVM☆25Updated 7 years ago
- Verification IP for SPI protocol☆20Updated 5 years ago
- UVM VIP architecture generator☆20Updated 5 years ago
- UVM Testbench For SystemVerilog Combinator Implementation☆56Updated 8 years ago
- Verification IP for APB protocol☆71Updated 4 years ago
- AXI master to AHB slave, support INCR/WRAP, out of standing, do not advanced feature such as support out of order, retry, split, etc☆41Updated 3 years ago
- Advance UVM testbench with DPI integration, Assertions, Functional Coverage andHierarchical Sequence☆37Updated 5 years ago
- Generate SystemVerilog/UVM block level testbench setup with python script☆10Updated 8 years ago
- a very simple risc_cpu verification demo with uvm☆26Updated 6 years ago
- UVM resource from github, run simulation use YASAsim flow☆30Updated 5 years ago
- Simple AMBA VIP, Include axi/ahb/apb☆27Updated last year
- This repository contains an example of the use of UVM Register Abstraction Layer in a verification of a simple APB DUT.☆46Updated 5 years ago
- UVM examples☆11Updated 10 years ago
- ☆38Updated 10 years ago
- A UVM verification with a APB BFM (Bus functional model), connected to two write-only DAC and two read-only ADC slaves. The sequence gene…☆15Updated 7 years ago
- System Verilog and Emulation. Written all the five channels.☆34Updated 8 years ago
- Use ORDT and systemRDL tools to generate C/Verilog header files, register RTL, UVM register models, and docs from compiled SystemRDL.☆70Updated 5 years ago
- ☆14Updated last year
- Synchronous FIFO design & verification using systemVerilog Assertions☆17Updated 4 years ago