Alternatives and similar repositories for uvm_candy_lover

Users that are interested in uvm_candy_lover are comparing it to the libraries listed below

• hengfengzhang / soc
  soc integration script and integration smoke script
  ☆24Updated 3 years ago
• nguyenquanicd / UvmEnvUartApb
  This is the UVM environment for UART-APB IP core. This environment contains full UVM components. It is only used for studing and invetiga…
  ☆24Updated 6 years ago
• seabeam / yuu_apb
  UVM APB VIP, part of AMBA3&AMBA4 feature supported
  ☆33Updated 5 years ago
• zhajio1988 / Open_RegModel
  Use ORDT and systemRDL tools to generate C/Verilog header files, register RTL, UVM register models, and docs from compiled SystemRDL.
  ☆73Updated 6 years ago
• seabeam / yuu_register_productor
  UVM register utility generation by inputting xls table
  ☆39Updated 2 years ago
• Lampro-Mellon / apb-uart-uvm-env
  ☆48Updated 2 years ago
• wenxuan-hu / SSRL_work
  work in SSRL, SOC/NOC/Chiplet Design, DDR/UCIe/PCIe, UVM Framework
  ☆37Updated 3 years ago
• letitbe0201 / AXI-DMA-master-verification
  ☆26Updated 4 years ago
• dpc525 / uvm_tb_gen
  generate UVM testbench using python
  ☆28Updated 7 years ago
• xdesigns / 4way-cache
  Verilog cache implementation of 4-way FIFO 16k Cache
  ☆20Updated 13 years ago
• zhajio1988 / ExtremeDV_UVM
  UVM resource from github, run simulation use YASAsim flow
  ☆32Updated 5 years ago
• KasuganoSoraaa / simple-AXI2AHB-bridge
  AXI master to AHB slave, support INCR/WRAP, out of standing, do not advanced feature such as support out of order, retry, split, etc
  ☆42Updated 3 years ago
• muneebullashariff / spi_vip
  Verification IP for SPI protocol
  ☆19Updated 5 years ago
• seabeam / yuu_vip_gen
  UVM VIP architecture generator
  ☆20Updated 5 years ago
• darwinbeing / EasierUVM
  DOULOS Easier UVM Code Generator
  ☆37Updated 8 years ago
• hjking / uvm_gen
  UVM Generator
  ☆48Updated last year
• smartfoxdata / uvm_axi4lite
  uvm_axi4lite is a uvm package for modeling and verifying AXI4 Lite protocol
  ☆31Updated 11 months ago
• muneebullashariff / axi4_vip
  Verification IP for APB protocol
  ☆73Updated 5 years ago
• jiacaiyuan / uvm-generator
  UVM Auto Generate ; Verify Project Build; Verilog Instance
  ☆35Updated 5 years ago
• MushroomZQ / RISC_VERIF_DEMO_0
  a very simple risc_cpu verification demo with uvm
  ☆26Updated 6 years ago
• MilanKubavat / TestbenchGenerator
  Generate SystemVerilog/UVM block level testbench setup with python script
  ☆10Updated 8 years ago
• muneebullashariff / i2c_vip
  Verification IP for I2C protocol
  ☆50Updated 4 years ago
• wanderingnail / AXI_DMA
  ☆20Updated 3 years ago
• muneebullashariff / apb_vip
  Verification IP for APB protocol
  ☆30Updated 5 years ago
• jinz2014 / UVM
  UVM examples
  ☆13Updated 10 years ago
• nelsoncsc / easyUVM
  A simple UVM example with DPI
  ☆45Updated 8 years ago
• zhajio1988 / YasaUvk
  UVM verification kits which uses YASA as simulation script
  ☆17Updated 6 years ago
• praveenkhemalapure / DDR3-controller-verification
  DDR3 function verification environment in UVM
  ☆26Updated 7 years ago
• holdenQWER / systemverilog_design_pattern
  The source code of blog
  ☆14Updated 4 years ago
• luuvish / amba3-vip
  amba3 apb/axi vip
  ☆52Updated 10 years ago