zhajio1988 / uvm_candy_lover
UVM candy lover testbench which uses YASA as simulation script
☆16Updated 4 years ago
Alternatives and similar repositories for uvm_candy_lover:
Users that are interested in uvm_candy_lover are comparing it to the libraries listed below
- ☆36Updated last year
- generate UVM testbench using python☆27Updated 6 years ago
- UVM register utility generation by inputting xls table☆35Updated last year
- UVM APB VIP, part of AMBA3&AMBA4 feature supported☆31Updated 4 years ago
- UVM resource from github, run simulation use YASAsim flow☆27Updated 4 years ago
- UVM examples☆10Updated 9 years ago
- ☆24Updated 3 years ago
- UVM verification kits which uses YASA as simulation script☆13Updated 5 years ago
- Verification IP for APB protocol☆57Updated 4 years ago
- AHB-APB UVM Verification Environment☆17Updated 9 years ago
- UVM VIP architecture generator☆19Updated 4 years ago
- this is an AHB to APB bridge with Synopsys VIP based test enviroment. RTL can be found from UVM website.☆16Updated 10 years ago
- Verification IP for SPI protocol☆17Updated 4 years ago
- System verilog register model for uvm testbenches.☆18Updated 6 years ago
- work in SSRL, SOC/NOC/Chiplet Design, DDR/UCIe/PCIe, UVM Framework☆30Updated 2 years ago
- A UVM verification with a APB BFM (Bus functional model), connected to two write-only DAC and two read-only ADC slaves. The sequence gene…☆14Updated 6 years ago
- UART design in SV and verification using UVM and SV☆40Updated 5 years ago
- Verification IP for APB protocol☆26Updated 4 years ago
- This is verification project that we are writing SystemVerilog code to verify 8/16/32 bit SDRAM Controller Which is Originally developed …☆21Updated 7 years ago
- DDR3 function verification environment in UVM☆23Updated 6 years ago
- A Verification Platform for UDP Protocol Ethernet Module wrapped with AXI and APB bus based on UVM☆24Updated 2 years ago
- ☆17Updated 3 years ago
- The UART (Universal Asynchronous Receiver/Transmitter) core provides serial communication capabilities, which allow communication with a …☆17Updated 3 years ago
- UVM testbench environment consisting of an APB driver, high level SPI controller model, and SPI verification testbench based upon an LPC2…☆8Updated last month
- uvm_axi4lite is a uvm package for modeling and verifying AXI4 Lite protocol☆16Updated 2 weeks ago
- Use ORDT and systemRDL tools to generate C/Verilog header files, register RTL, UVM register models, and docs from compiled SystemRDL.☆66Updated 5 years ago
- General Purpose I/O agent written in UVM☆15Updated 7 years ago
- Sample UVM code for axi ram dut☆30Updated 3 years ago
- UVM Auto Generate ; Verify Project Build; Verilog Instance☆33Updated 4 years ago
- an open source uvm verification platform for e200 (riscv)☆26Updated 6 years ago