zhajio1988 / uvm_candy_lover

Related projects: ⓘ

• zhajio1988 / YasaUvk
  UVM verification kits which uses YASA as simulation script
  ☆13Updated 4 years ago
• seabeam / yuu_apb
  UVM APB VIP, part of AMBA3&AMBA4 feature supported
  ☆28Updated 4 years ago
• hengfengzhang / soc
  soc integration script and integration smoke script
  ☆21Updated 2 years ago
• seabeam / yuu_vip_gen
  UVM VIP architecture generator
  ☆16Updated 4 years ago
• jiacaiyuan / uvm-generator
  UVM Auto Generate ; Verify Project Build; Verilog Instance
  ☆30Updated 4 years ago
• seabeam / yuu_register_productor
  UVM register utility generation by inputting xls table
  ☆33Updated last year
• dpc525 / uvm_tb_gen
  generate UVM testbench using python
  ☆26Updated 6 years ago
• wenxuan-hu / SSRL_work
  work in SSRL, SOC/NOC/Chiplet Design, DDR/UCIe/PCIe, UVM Framework
  ☆24Updated last year
• Gateway91 / AHB-APB_Bridge_UVM_Env
  AHB-APB UVM Verification Environment
  ☆17Updated 9 years ago
• muneebullashariff / apb_vip
  Verification IP for APB protocol
  ☆23Updated 4 years ago
• techvinodreddy / UART-IP-CORE16550A-Verification-UVM
  The UART (Universal Asynchronous Receiver/Transmitter) core provides serial communication capabilities, which allow communication with a …
  ☆15Updated 3 years ago
• zhajio1988 / ExtremeDV_UVM
  UVM resource from github, run simulation use YASAsim flow
  ☆24Updated 4 years ago
• muneebullashariff / axi4_vip
  Verification IP for APB protocol
  ☆55Updated 3 years ago
• openhwgroup / core-v-mcu-uvm
  CORE-V MCU UVM Environment and Test Bench
  ☆16Updated 2 months ago
• Lampro-Mellon / apb-uart-uvm-env
  ☆33Updated 10 months ago
• panweitao / riscvv
  an open source uvm verification platform for e200 (riscv)
  ☆26Updated 6 years ago
• avashist003 / UVM_Verification
  Advance UVM testbench with DPI integration, Assertions, Functional Coverage andHierarchical Sequence
  ☆27Updated 4 years ago
• smartfoxdata / uvm_axi4lite
  uvm_axi4lite is a uvm package for modeling and verifying AXI4 Lite protocol
  ☆14Updated 7 years ago
• zhouchuanrui / JSONinSV
  JSON lib in Systemverilog
  ☆42Updated 2 years ago
• muneebullashariff / spi_vip
  Verification IP for SPI protocol
  ☆16Updated 4 years ago
• mingzhang952 / uvm_auto
  uvm auto generator
  ☆22Updated 6 years ago
• letitbe0201 / AXI-DMA-master-verification
  ☆20Updated 3 years ago
• muneebullashariff / i2c_vip
  Verification IP for I2C protocol
  ☆36Updated 3 years ago
• JakodYuan / SVK-AMBA-VIP
  Simple AMBA VIP, Include axi/ahb/apb
  ☆13Updated 2 months ago
• nahidrn / axi_vip_master
  Sample UVM code for axi ram dut
  ☆27Updated 2 years ago
• yvnr4you / AMBA_AXI3
  System Verilog and Emulation. Written all the five channels.
  ☆31Updated 7 years ago
• darthsider / UART
  UART design in SV and verification using UVM and SV
  ☆38Updated 4 years ago
• JoseIuri / UVM-APB_RAL
  This repository contains an example of the use of UVM Register Abstraction Layer in a verification of a simple APB DUT.
  ☆33Updated 4 years ago
• zhajio1988 / Open_RegModel
  Use ORDT and systemRDL tools to generate C/Verilog header files, register RTL, UVM register models, and docs from compiled SystemRDL.
  ☆66Updated 4 years ago
• doswellf / combinator-uvm
  UVM Testbench For SystemVerilog Combinator Implementation
  ☆50Updated 7 years ago