Alternatives and similar repositories for uvm_candy_lover:

Users that are interested in uvm_candy_lover are comparing it to the libraries listed below

• hengfengzhang / soc
  soc integration script and integration smoke script
  ☆21Updated 2 years ago
• dpc525 / uvm_tb_gen
  generate UVM testbench using python
  ☆27Updated 7 years ago
• seabeam / yuu_apb
  UVM APB VIP, part of AMBA3&AMBA4 feature supported
  ☆31Updated 4 years ago
• Gateway91 / AHB-APB_Bridge_UVM_Env
  AHB-APB UVM Verification Environment
  ☆17Updated 9 years ago
• zhajio1988 / ExtremeDV_UVM
  UVM resource from github, run simulation use YASAsim flow
  ☆27Updated 4 years ago
• Lampro-Mellon / apb-uart-uvm-env
  ☆38Updated last year
• jiacaiyuan / uvm-generator
  UVM Auto Generate ; Verify Project Build; Verilog Instance
  ☆34Updated 4 years ago
• seabeam / yuu_vip_gen
  UVM VIP architecture generator
  ☆19Updated 4 years ago
• smartfoxdata / uvm_axi4lite
  uvm_axi4lite is a uvm package for modeling and verifying AXI4 Lite protocol
  ☆19Updated last month
• darthsider / UART
  UART design in SV and verification using UVM and SV
  ☆41Updated 5 years ago
• darwinbeing / EasierUVM
  DOULOS Easier UVM Code Generator
  ☆31Updated 7 years ago
• imokanj / gpio_agent
  General Purpose I/O agent written in UVM
  ☆15Updated 7 years ago
• zhajio1988 / YasaUvk
  UVM verification kits which uses YASA as simulation script
  ☆13Updated 5 years ago
• PacoReinaCampo / SoC-DV
  System on Chip verified with UVM/OSVVM/FV
  ☆24Updated this week
• panweitao / riscvv
  an open source uvm verification platform for e200 (riscv)
  ☆26Updated 6 years ago
• jinz2014 / UVM
  UVM examples
  ☆10Updated 9 years ago
• muneebullashariff / axi4_vip
  Verification IP for APB protocol
  ☆60Updated 4 years ago
• techvinodreddy / UART-IP-CORE16550A-Verification-UVM
  The UART (Universal Asynchronous Receiver/Transmitter) core provides serial communication capabilities, which allow communication with a …
  ☆17Updated 3 years ago
• Mohamed-Younis / SPI-UVM-Testbench
  ☆19Updated 3 years ago
• seabeam / yuu_register_productor
  UVM register utility generation by inputting xls table
  ☆36Updated last year
• fighter212 / ahb2apb
  this is an AHB to APB bridge with Synopsys VIP based test enviroment. RTL can be found from UVM website.
  ☆16Updated 10 years ago
• muneebullashariff / spi_vip
  Verification IP for SPI protocol
  ☆17Updated 4 years ago
• wenxuan-hu / SSRL_work
  work in SSRL, SOC/NOC/Chiplet Design, DDR/UCIe/PCIe, UVM Framework
  ☆31Updated 2 years ago
• imokanj / clk_rst_agent
  UVM Clock and Reset Agent
  ☆13Updated 7 years ago
• holdenQWER / systemverilog_design_pattern
  The source code of blog
  ☆14Updated 3 years ago
• JoseIuri / UVM_Python_UVMC
  This repository contains an example of the connection between an UVM Testbench and a Python reference model using UVM Connect from Mentor…
  ☆15Updated 5 years ago
• letitbe0201 / AXI-DMA-master-verification
  ☆25Updated 3 years ago
• muguang123 / AXI_Verification
  Verification AXI-4 bus standard using UVM and System Verilog
  ☆15Updated 6 years ago
• mingzhang952 / uvm_auto
  uvm auto generator
  ☆24Updated 6 years ago
• hjking / uvm_gen
  UVM Generator
  ☆44Updated 10 months ago