cam-n / human-detection-hog-svmLinks
A human detection system is developed on Matlab and FPGA: The 130x66 RGB pixels of static input image was attracted features and classified with/without human by using Histogram of Oriented Gradient (HOG) and Support Vector Machine (SVM) algorithm, respectively.
☆12Updated 2 years ago
Alternatives and similar repositories for human-detection-hog-svm
Users that are interested in human-detection-hog-svm are comparing it to the libraries listed below
Sorting:
- 位宽和深度可定制的异步FIFO☆13Updated last year
- DMA core compatible with AHB3-Lite☆10Updated 6 years ago
- 基于FPGA的FFT☆19Updated 6 years ago
- ☆20Updated 3 years ago
- Ultra High Performance AXI4-based Direct Memory Access (DMA) Controller. This project was an interview assignment. Work in Progress.☆12Updated last year
- ☆16Updated 6 years ago
- A Direct Memory Access Controller (DMAC) with AHB-lite bus interface☆15Updated last year
- this is an AHB to APB bridge with Synopsys VIP based test enviroment. RTL can be found from UVM website.☆18Updated 11 years ago
- ☆11Updated 2 years ago
- AHB-lite, AHB-APB bridge and extended APB side architecture in SystemVerilog☆16Updated 2 years ago
- - A 1X3 Router (capable of routing the data packets to three different clients form a single source network) was designed, including a re…☆11Updated 6 years ago
- Router 1 x 3 verilog implementation☆14Updated 4 years ago
- AHB/APB SRAM Inf, VCS&Verdi Sim.☆14Updated 3 years ago
- FIR,FFT based on Verilog☆13Updated 7 years ago
- Simple demo showing how to use the ping pong FIFO☆15Updated 9 years ago
- ☆26Updated 4 years ago
- Verilog code that does 2D Low Pass Filter on a greyscale image☆10Updated 10 years ago
- Verification IP for Watchdog☆12Updated 4 years ago
- Universal Asynchronous Receiver/Transmitter (UART) with FIFOs Soft IP☆13Updated 9 months ago
- 七路图像在FPGA中实现拼接,代码会不断添加进来。☆28Updated 4 years ago
- UVM verification platform for DW_apb_i2c IP core(Master Mode)☆11Updated 2 years ago
- ☆12Updated 10 years ago
- CORDIC VLSI-IP for deep learning activation functions☆15Updated 6 years ago
- AXI4 with a FIFO integrated with VIP☆22Updated last year
- ☆17Updated 10 years ago
- OpenExSys_NoC a mesh-based network on chip IP.☆18Updated last year
- verification of simple axi-based cache☆18Updated 6 years ago
- ☆10Updated 5 years ago
- CS533 Course Project (ongoing) - Exploring Parallel Architectures for Neural Processing Unit Implementations☆19Updated 8 years ago
- UVM Testbench for synchronus fifo☆17Updated 5 years ago