Alternatives and similar repositories for human-detection-hog-svm:

Users that are interested in human-detection-hog-svm are comparing it to the libraries listed below

• vfinotti / ahb3lite_dma
  DMA core compatible with AHB3-Lite
  ☆10Updated 5 years ago
• wbbbbbb123 / Sram-controller-design-based-on-AHB-bus
  ☆18Updated 2 years ago
• Verdvana / Async_FIFO
  位宽和深度可定制的异步FIFO
  ☆13Updated 9 months ago
• DeamonYang / FPGA_FFT
  基于FPGA的FFT
  ☆12Updated 6 years ago
• mhhai / ImageStitchBasedOnFPGA
  七路图像在FPGA中实现拼接，代码会不断添加进来。
  ☆24Updated 3 years ago
• Jon3Y / AMBA
  AHB/APB SRAM Inf, VCS&Verdi Sim.
  ☆12Updated 2 years ago
• fighter212 / ahb2apb
  this is an AHB to APB bridge with Synopsys VIP based test enviroment. RTL can be found from UVM website.
  ☆16Updated 10 years ago
• nguyenquanicd / AllArbiterRTLCode
  RTL code of some arbitration algorithm
  ☆13Updated 5 years ago
• srishis / DMA8237A_VERIF
  Verification of DMA Controller for 8086 Microprocessor Systems using OO Test bench
  ☆11Updated 4 years ago
• srohit0 / CORDIC
  CORDIC VLSI-IP for deep learning activation functions
  ☆14Updated 5 years ago
• letitbe0201 / AXI-DMA-master-verification
  ☆25Updated 3 years ago
• edwardclin2003 / LowPassFilterImageFPGA
  Verilog code that does 2D Low Pass Filter on a greyscale image
  ☆10Updated 9 years ago
• wbbbbbb123 / UVM-based-AHB-bus-SRAM-controller-design-verification-platform-design
  ☆14Updated 2 years ago
• mfkiwl / E203_dma
  ☆9Updated 4 years ago
• tom-urkin / AMBA
  AHB-lite, AHB-APB bridge and extended APB side architecture in SystemVerilog
  ☆13Updated last year
• Jefferyy-Peng / AXI_DMA_CONTROLLER
  ☆11Updated 2 years ago
• efabless / raptor_soc_template
  Raptor is an SoC Design Template based on Arm Cortex M0 or M3 core.
  ☆18Updated 5 years ago
• yuhsaun-t / NPU-Architecture
  CS533 Course Project (ongoing) - Exploring Parallel Architectures for Neural Processing Unit Implementations
  ☆19Updated 7 years ago
• JoseIuri / axi4lite2uart
  This IP provides a bridge between UART signals and the Advanced Microcontroller Bus Architecture (AMBA®) AXI4 Lite interface.
  ☆18Updated 6 years ago
• visky2096 / AHB-to-I2C
  Attempt to setup a bridge between AHB and I2C by constructing dedicated modules of AHB master , AHB slave , APB master , APB slave, I2C m…
  ☆21Updated 6 years ago
• open-dv / dma_axi
  ☆16Updated 5 years ago
• fengyulin1996 / Verilog-DSP
  FIR，FFT based on Verilog
  ☆13Updated 7 years ago
• kdurant / axi-ddr3
  学习AXI接口，以及xilinx DDR3 IP使用
  ☆36Updated 8 years ago
• yayouz / CNN-accelerator
  DMA controller for CNN accelerator
  ☆13Updated 7 years ago
• Youssefmdany / Design-and-UVM-TB-of-RISC-V-Microprocessor
  Design and UVM-TB of RISC -V Microprocessor
  ☆15Updated 9 months ago
• CospanDesign / verilog_ppfifo_demo
  Simple demo showing how to use the ping pong FIFO
  ☆14Updated 8 years ago
• apriya-ram / AXI_FIFO_BFM
  AXI4 with a FIFO integrated with VIP
  ☆16Updated last year
• wanderingnail / AXI_DMA
  ☆19Updated 2 years ago
• muneebullashariff / pulpino_soc_uvm_testbench
  UVM testbench for verifying the Pulpino SoC
  ☆13Updated 5 years ago
• shalan / QSPI_XIP_CTRL_DMC
  Quad SPI Flash XIP Controller with a direct mapped cache
  ☆11Updated 4 years ago