Alternatives and similar repositories for human-detection-hog-svm:

Users that are interested in human-detection-hog-svm are comparing it to the libraries listed below

• Verdvana / Async_FIFO
  位宽和深度可定制的异步FIFO
  ☆13Updated 10 months ago
• Jon3Y / AMBA
  AHB/APB SRAM Inf, VCS&Verdi Sim.
  ☆12Updated 2 years ago
• mfkiwl / E203_dma
  ☆9Updated 4 years ago
• edwardclin2003 / LowPassFilterImageFPGA
  Verilog code that does 2D Low Pass Filter on a greyscale image
  ☆10Updated 9 years ago
• mhhai / ImageStitchBasedOnFPGA
  七路图像在FPGA中实现拼接，代码会不断添加进来。
  ☆24Updated 3 years ago
• vfinotti / ahb3lite_dma
  DMA core compatible with AHB3-Lite
  ☆10Updated 6 years ago
• yayouz / CNN-accelerator
  DMA controller for CNN accelerator
  ☆13Updated 7 years ago
• srishis / DMA8237A_VERIF
  Verification of DMA Controller for 8086 Microprocessor Systems using OO Test bench
  ☆11Updated 4 years ago
• wbbbbbb123 / Sram-controller-design-based-on-AHB-bus
  ☆18Updated 2 years ago
• DeamonYang / FPGA_FFT
  基于FPGA的FFT
  ☆13Updated 6 years ago
• fighter212 / ahb2apb
  this is an AHB to APB bridge with Synopsys VIP based test enviroment. RTL can be found from UVM website.
  ☆16Updated 10 years ago
• apriya-ram / AXI_FIFO_BFM
  AXI4 with a FIFO integrated with VIP
  ☆16Updated last year
• letitbe0201 / AXI-DMA-master-verification
  ☆25Updated 3 years ago
• tom-urkin / AMBA
  AHB-lite, AHB-APB bridge and extended APB side architecture in SystemVerilog
  ☆14Updated last year
• kdurant / axi-ddr3
  学习AXI接口，以及xilinx DDR3 IP使用
  ☆36Updated 8 years ago
• kumarswamy12 / ROUTER-1-3
  verification of the basic router protocol with UVM testbech //INCLUDED WITH RTL
  ☆12Updated 6 years ago
• mnmhdanas / Router-1-x-3-
  Router 1 x 3 verilog implementation
  ☆13Updated 3 years ago
• yangjiekai / backpropagation_NN_FPGA_implementation
  This is the final project for the BP NN FPGA implementation
  ☆11Updated 8 years ago
• zhongguanggong / ggz
  使用FPGA实现CNN模型
  ☆13Updated 5 years ago
• marshall-999 / UVMReference
  This is a open source project from UVM Community and it is based on an Ethernet Switch System-on-Chip (SoC).
  ☆12Updated 3 years ago
• Youssefmdany / Design-and-UVM-TB-of-RISC-V-Microprocessor
  Design and UVM-TB of RISC -V Microprocessor
  ☆17Updated 9 months ago
• muneebullashariff / pulpino_soc_uvm_testbench
  UVM testbench for verifying the Pulpino SoC
  ☆13Updated 5 years ago
• yuhsaun-t / NPU-Architecture
  CS533 Course Project (ongoing) - Exploring Parallel Architectures for Neural Processing Unit Implementations
  ☆19Updated 7 years ago
• wbbbbbb123 / UVM-based-AHB-bus-SRAM-controller-design-verification-platform-design
  ☆14Updated 2 years ago
• Nitcloud / Image_sim
  基于FPGA的图像处理模块（出自于crazybingo）（将部分IP换为纯Verilog用于跨平台移植）
  ☆46Updated 4 years ago
• fangyzh26 / FIFO
  包括同步FIFO（输入输出位宽相同），异步FIFO（输入输出位宽相同），异步FIFO（能实现输出数据位宽是输入数据位宽的1/2或2倍）
  ☆20Updated 2 years ago
• CospanDesign / verilog_ppfifo_demo
  Simple demo showing how to use the ping pong FIFO
  ☆14Updated 8 years ago
• raiyyanfaisal09 / Router1X3_RTL_Design
  - A 1X3 Router (capable of routing the data packets to three different clients form a single source network) was designed, including a re…
  ☆10Updated 5 years ago
• open-dv / dma_axi
  ☆16Updated 5 years ago
• Jefferyy-Peng / AXI_DMA_CONTROLLER
  ☆11Updated 2 years ago