marsiau / PYNQ-RTL-SDR
A FPGA accelerated SDR receiver using PYNQ-Z2 board and RTL-SDR
☆20Updated 5 years ago
Alternatives and similar repositories for PYNQ-RTL-SDR:
Users that are interested in PYNQ-RTL-SDR are comparing it to the libraries listed below
- RFSoC Spectrum Analyser Module on PYNQ.☆76Updated 9 months ago
- JESD204B core for Migen/MiSoC☆36Updated 3 years ago
- Skeletal repository for GNU Radio WBFM implementation on Pynq board☆13Updated 7 years ago
- LiteX Accelerator Block for GNU Radio☆24Updated 3 years ago
- OscillatorIMP ecosystem for the digital characterization of ultrastable oscillators and Software Defined Radio (SDR) frontend processing☆54Updated 3 weeks ago
- Demonstration of Automatic Gain Control with PYNQ☆12Updated 2 years ago
- An RFSoC Frequency Planner developed using Python.☆25Updated last year
- PYNQ example of using the RFSoC as a QPSK/BPSK radio transceiver.☆35Updated last year
- Extensible FPGA control platform☆59Updated last year
- pynq framework for antsdr☆34Updated 10 months ago
- RFSoC2x2 board repo for PYNQ☆17Updated 2 years ago
- Fully pipelined Integer Scaled / Unscaled Radix-2 Forward/Inverse Fast Fourier Transform (FFT) IP-core for newest Xilinx FPGAs (Source la…☆83Updated 2 years ago
- Python productivity for RFSoC platforms☆66Updated 10 months ago
- Single Port RAM, Dual Port RAM, FIFO☆23Updated 2 years ago
- A demonstration showing how several components can be compsed to build a simulated spectrogram☆42Updated last year
- HDL code for a complex multiplier with AXI stream interface☆16Updated 2 years ago
- Altera Cyclone IV FPGA project for the PCIe LimeSDR board☆38Updated 2 years ago
- ☆41Updated last year
- Saturn SDR Radio: Xilinx FPGA and Raspberry Pi 4 CM☆40Updated last week
- Digital FM Radio Receiver for FPGA☆60Updated 9 years ago
- Notes on the Eclypse Z7 development board☆12Updated last month
- OscillatorIMP ecosystem FPGA IP sources☆27Updated 3 weeks ago
- ☆28Updated 5 years ago
- A ZipCPU based demonstration of the MAX1000 FPGA board☆21Updated 3 years ago
- Implementation and test of reusable sigma-delta A/D converters written in SystemVerilog on a MAX10 FPGA with minimal external components☆63Updated 3 years ago
- A collection of RFSoC introductory notebooks for PYNQ.☆20Updated 3 years ago
- VHDL PCIe Transceiver☆28Updated 4 years ago
- UART to AXI Stream interface written in VHDL☆16Updated 2 years ago
- VHDL Library for implementing common DSP functionality.☆27Updated 6 years ago
- LimeSDR XTRX gateware project.☆16Updated 2 months ago