Alternatives and similar repositories for uvm-tutorial-for-candy-lovers

Users that are interested in uvm-tutorial-for-candy-lovers are comparing it to the libraries listed below

• darwinbeing / EasierUVM
  DOULOS Easier UVM Code Generator
  ☆34Updated 8 years ago
• holdenQWER / systemverilog_design_pattern
  The source code of blog
  ☆14Updated 3 years ago
• zhajio1988 / uvm_candy_lover
  UVM candy lover testbench which uses YASA as simulation script
  ☆17Updated 5 years ago
• ptracton / AXI_BFM
  AXI4 BFM in Verilog
  ☆32Updated 8 years ago
• jiacaiyuan / uvm-generator
  UVM Auto Generate ; Verify Project Build; Verilog Instance
  ☆34Updated 5 years ago
• zhajio1988 / ExtremeDV_UVM
  UVM resource from github, run simulation use YASAsim flow
  ☆27Updated 5 years ago
• yvnr4you / AMBA_AXI3
  System Verilog and Emulation. Written all the five channels.
  ☆34Updated 8 years ago
• Practical-UVM-Step-By-Step / Practical-UVM-IEEE-Edition
  This is the repository for the IEEE version of the book
  ☆66Updated 4 years ago
• dpc525 / uvm_tb_gen
  generate UVM testbench using python
  ☆27Updated 7 years ago
• StanfordAHA / AhaM3SoC
  SoC Based on ARM Cortex-M3
  ☆32Updated last month
• panweitao / riscvv
  an open source uvm verification platform for e200 (riscv)
  ☆28Updated 7 years ago
• zhajio1988 / Open_RegModel
  Use ORDT and systemRDL tools to generate C/Verilog header files, register RTL, UVM register models, and docs from compiled SystemRDL.
  ☆69Updated 5 years ago
• smartfoxdata / uvm_axi4lite
  uvm_axi4lite is a uvm package for modeling and verifying AXI4 Lite protocol
  ☆22Updated 4 months ago
• hjking / uvm_gen
  UVM Generator
  ☆45Updated last year
• darthsider / UART
  UART design in SV and verification using UVM and SV
  ☆44Updated 5 years ago
• emwzq / example_uvm
  UVM实战随书源码
  ☆51Updated 6 years ago
• freecores / dma_ahb
  AHB DMA 32 / 64 bits
  ☆56Updated 10 years ago
• kdurant / axi-ddr3
  学习AXI接口，以及xilinx DDR3 IP使用
  ☆37Updated 8 years ago
• hengfengzhang / soc
  soc integration script and integration smoke script
  ☆22Updated 2 years ago
• zhouchuanrui / JSONinSV
  JSON lib in Systemverilog
  ☆43Updated 3 years ago
• xdesigns / 4way-cache
  Verilog cache implementation of 4-way FIFO 16k Cache
  ☆19Updated 12 years ago
• Juniper / simple_reg_model
  System verilog register model for uvm testbenches.
  ☆19Updated 6 years ago
• aignacio / axi_dma
  General Purpose AXI Direct Memory Access
  ☆51Updated last year
• muneebullashariff / apb_vip
  Verification IP for APB protocol
  ☆26Updated 4 years ago
• nelsoncsc / easyUVM
  A simple UVM example with DPI
  ☆40Updated 7 years ago
• funannoka / SoC-Design-DDR3-Controller
  DDR3 SDRAM Memory Controller Design & Synthesis using System Verilog
  ☆31Updated 6 years ago
• Ghonimo / Formal-Verification-of-an-AHB2APB-Bridge
  Assertion-Based Formal Verification of an AHB2APB bridge, featuring SystemVerilog assertions, RTL designs, and detailed documentation inc…
  ☆19Updated last year
• letitbe0201 / AXI-DMA-master-verification
  ☆25Updated 4 years ago
• zhajio1988 / YasaUvk
  UVM verification kits which uses YASA as simulation script
  ☆13Updated 5 years ago
• doswellf / combinator-uvm
  UVM Testbench For SystemVerilog Combinator Implementation
  ☆55Updated 8 years ago