Alternatives and similar repositories for simple_reg_model

Users that are interested in simple_reg_model are comparing it to the libraries listed below

• seabeam / yuu_register_productor
  UVM register utility generation by inputting xls table
  ☆39Updated 2 years ago
• zhajio1988 / YasaUvk
  UVM verification kits which uses YASA as simulation script
  ☆15Updated 5 years ago
• amiq-consulting / amiq_apb
  SystemVerilog VIP for AMBA APB protocol
  ☆79Updated 3 years ago
• doswellf / combinator-uvm
  UVM Testbench For SystemVerilog Combinator Implementation
  ☆56Updated 8 years ago
• hjking / uvm_gen
  UVM Generator
  ☆47Updated last year
• Practical-UVM-Step-By-Step / Practical-UVM-IEEE-Edition
  This is the repository for the IEEE version of the book
  ☆71Updated 5 years ago
• jiacaiyuan / uvm-generator
  UVM Auto Generate ; Verify Project Build; Verilog Instance
  ☆35Updated 5 years ago
• JoseIuri / UVM-APB_RAL
  This repository contains an example of the use of UVM Register Abstraction Layer in a verification of a simple APB DUT.
  ☆45Updated 5 years ago
• zhajio1988 / Open_RegModel
  Use ORDT and systemRDL tools to generate C/Verilog header files, register RTL, UVM register models, and docs from compiled SystemRDL.
  ☆70Updated 5 years ago
• luuvish / amba3-vip
  amba3 apb/axi vip
  ☆51Updated 10 years ago
• zhajio1988 / YASA
  Yet Another Simulation Architecture
  ☆76Updated 5 years ago
• seabeam / yuu_apb
  UVM APB VIP, part of AMBA3&AMBA4 feature supported
  ☆32Updated 5 years ago
• jerralph / riscv-vip
  For pre-silicon developers of RISC-V systems, riscv-vip is a SystemVerilog project that helps with pre-si verification and debug
  ☆64Updated 4 years ago
• Lampro-Mellon / apb-uart-uvm-env
  ☆43Updated last year
• andres-mancera / ethernet_10ge_mac_SV_UVM_tb
  SystemVerilog-based UVM testbench for an Ethernet 10GE MAC core
  ☆149Updated 7 years ago
• darthsider / UART
  UART design in SV and verification using UVM and SV
  ☆49Updated 5 years ago
• seabeam / yuu_ahb
  UVM AHB VIP
  ☆87Updated 3 weeks ago
• Ghonimo / Formal-Verification-of-an-AHB2APB-Bridge
  Assertion-Based Formal Verification of an AHB2APB bridge, featuring SystemVerilog assertions, RTL designs, and detailed documentation inc…
  ☆20Updated last year
• marcoz001 / axi-uvm
  yet another AXI testbench repo. ;) This is for my UVM practice. https://marcoz001.github.io/axi-uvm/
  ☆128Updated 7 years ago
• dpc525 / uvm_tb_gen
  generate UVM testbench using python
  ☆28Updated 7 years ago
• troyguo / dvcon_download
  Download proccedings from DVCon
  ☆22Updated 4 years ago
• muneebullashariff / axi4_vip
  Verification IP for APB protocol
  ☆70Updated 4 years ago
• techvinodreddy / UART-IP-CORE16550A-Verification-UVM
  The UART (Universal Asynchronous Receiver/Transmitter) core provides serial communication capabilities, which allow communication with a …
  ☆17Updated 4 years ago
• darwinbeing / EasierUVM
  DOULOS Easier UVM Code Generator
  ☆36Updated 8 years ago
• wenxuan-hu / SSRL_work
  work in SSRL, SOC/NOC/Chiplet Design, DDR/UCIe/PCIe, UVM Framework
  ☆35Updated 2 years ago
• dovstamler / uvm_agents
  UVM agents
  ☆83Updated 8 years ago
• mingzhang952 / uvm_auto
  uvm auto generator
  ☆24Updated 7 years ago
• muneebullashariff / i2c_vip
  Verification IP for I2C protocol
  ☆49Updated 4 years ago
• mayurkubavat / UVM-Examples
  UVM examples and projects
  ☆145Updated 3 months ago
• seabeam / yuu_vip_gen
  UVM VIP architecture generator
  ☆20Updated 5 years ago