Alternatives and similar repositories for simple_reg_model

Users that are interested in simple_reg_model are comparing it to the libraries listed below

• seabeam / yuu_register_productor
  UVM register utility generation by inputting xls table
  ☆36Updated last year
• zhajio1988 / YasaUvk
  UVM verification kits which uses YASA as simulation script
  ☆13Updated 5 years ago
• jiacaiyuan / uvm-generator
  UVM Auto Generate ; Verify Project Build; Verilog Instance
  ☆34Updated 5 years ago
• mingzhang952 / uvm_auto
  uvm auto generator
  ☆23Updated 6 years ago
• seabeam / yuu_vip_gen
  UVM VIP architecture generator
  ☆19Updated 4 years ago
• doswellf / combinator-uvm
  UVM Testbench For SystemVerilog Combinator Implementation
  ☆54Updated 8 years ago
• dpc525 / uvm_tb_gen
  generate UVM testbench using python
  ☆27Updated 7 years ago
• hjking / uvm_gen
  UVM Generator
  ☆45Updated last year
• kaushalmodi / custom_uvm_report_server
  Customized UVM Report Server
  ☆40Updated 5 years ago
• avashist003 / UVM_Verification
  Advance UVM testbench with DPI integration, Assertions, Functional Coverage andHierarchical Sequence
  ☆32Updated 4 years ago
• luuvish / amba3-vip
  amba3 apb/axi vip
  ☆49Updated 10 years ago
• troyguo / dvcon_download
  Download proccedings from DVCon
  ☆22Updated 3 years ago
• darthsider / UART
  UART design in SV and verification using UVM and SV
  ☆44Updated 5 years ago
• seabeam / yuu_apb
  UVM APB VIP, part of AMBA3&AMBA4 feature supported
  ☆31Updated 4 years ago
• zhajio1988 / ExtremeDV_UVM
  UVM resource from github, run simulation use YASAsim flow
  ☆27Updated 5 years ago
• JoseIuri / UVM-APB_RAL
  This repository contains an example of the use of UVM Register Abstraction Layer in a verification of a simple APB DUT.
  ☆39Updated 4 years ago
• Lampro-Mellon / apb-uart-uvm-env
  ☆40Updated last year
• Mohamed-Younis / SPI-UVM-Testbench
  ☆22Updated 4 years ago
• darwinbeing / EasierUVM
  DOULOS Easier UVM Code Generator
  ☆34Updated 8 years ago
• nahidrn / axi_vip_master
  Sample UVM code for axi ram dut
  ☆33Updated 3 years ago
• taichi-ishitani / tvip-apb
  Verification IP for AMBA APB Protocol
  ☆29Updated last year
• jerralph / riscv-vip
  For pre-silicon developers of RISC-V systems, riscv-vip is a SystemVerilog project that helps with pre-si verification and debug
  ☆60Updated 4 years ago
• muguang123 / AXI_Verification
  Verification AXI-4 bus standard using UVM and System Verilog
  ☆15Updated 7 years ago
• zhouchuanrui / JSONinSV
  JSON lib in Systemverilog
  ☆43Updated 3 years ago
• yvnr4you / SDRAM-Verification
  This is verification project that we are writing SystemVerilog code to verify 8/16/32 bit SDRAM Controller Which is Originally developed …
  ☆25Updated 8 years ago
• imokanj / gpio_agent
  General Purpose I/O agent written in UVM
  ☆15Updated 7 years ago
• muneebullashariff / axi4_vip
  Verification IP for APB protocol
  ☆66Updated 4 years ago
• amiq-consulting / amiq_apb
  SystemVerilog VIP for AMBA APB protocol
  ☆74Updated 3 years ago
• uvmdebug / uvm_debug
  UVM interactive debug library
  ☆32Updated 8 years ago
• VimfulDang / APB-SPI-Controller-Verification
  UVM testbench environment consisting of an APB driver, high level SPI controller model, and SPI verification testbench based upon an LPC2…
  ☆12Updated 5 months ago