Deverne-labs / TinyML-ZyboLinks
This repository is a collection of designs invloving FPGAs and AI technologies.
☆14Updated 2 years ago
Alternatives and similar repositories for TinyML-Zybo
Users that are interested in TinyML-Zybo are comparing it to the libraries listed below
Sorting:
- A 32 bit RISCV Based SOC with QSpi , Uart and 8 bit SDRAM Controller tagetted to efebless shuttle program☆20Updated 2 years ago
- An SPI to AXI4-lite bridge for easy interfacing of airhdl register banks with any microcontroller.☆48Updated last year
- A compact, configurable RISC-V core☆11Updated 3 months ago
- Quick'n'dirty FuseSoC+cocotb example☆18Updated 7 months ago
- The Open Source Hardware Accelerator for Efficient Neural Network Inference☆46Updated this week
- This repo contain the PY-UVM Framework for different RISC-V Cores☆31Updated last year
- This repository contains the Simple As Possible Floating Point Unit design based on the IEEE-754 Standard.☆18Updated 2 years ago
- Multi-Processor System on Chip verified with UVM/OSVVM/FV☆31Updated last month
- ☆41Updated 3 years ago
- Educational verilog library that supports IEEE754 floating point arithmetic with a parametrizable mantissa and exponent☆28Updated 3 months ago
- ☆36Updated 2 years ago
- Solving Sudokus using open source formal verification tools☆17Updated 2 years ago
- VSDBabySoC is a small mixed-signal SoC including PLL, DAC, and a RISCV-based processor named RVMYTH.☆43Updated 3 years ago
- ☆32Updated 5 months ago
- RPHAX provides a quick automation flow to develop and prototype hardware accelerators on Xilinx FPGAs. Currently, the framework has suppo…☆19Updated 2 years ago
- Modular SRAM-based 2D hierarchical-search Binary Content Addressable Memory (2D-BCAM)☆20Updated 7 months ago
- An open source, parameterized SystemVerilog digital hardware IP library☆27Updated last year
- Verilog HDL implementation of SDRAM controller and SDRAM model☆27Updated last year
- ☆41Updated last year
- SoC Based on ARM Cortex-M3☆32Updated last month
- tools to help make the most of the limited space we have on the Google sponsored Efabless shuttles☆36Updated 2 years ago
- The verilog code together with cocotb testbench of BFU unit of a DIF FFT processor☆15Updated 2 years ago
- Design of 1024x32 SRAM (32Kbits) using OpenRAM and SKY130 PDKs with operating voltage of 1.8V and access time < 2.5ns☆70Updated 4 years ago
- SoCGen is a tool that automates SoC design by taking in a JSON description of the system and producing the final GDS-II. SoCGen supports …☆38Updated 4 years ago
- Verilog RTL Design☆40Updated 3 years ago
- Wishbone interconnect utilities☆41Updated 4 months ago
- Demo of how to use https://github.com/openXC7 tools (yosys+nextpnr-xilinx) to implement the HW side of a custom SoC with RISC-V CPU & our…☆27Updated 4 months ago
- The open- MSP430 is an open-source 16-bit microcontroller core written in Verilog, that is compatible with the Texas Instruments MSP430 m…☆15Updated 3 years ago
- A tool that converts SystemVerilog to Verilog. Uses Design Compiler, so it is 100% compatible.☆42Updated 2 years ago
- WISHBONE Interconnect☆11Updated 7 years ago