Alternatives and similar repositories for TinyML-Zybo:

Users that are interested in TinyML-Zybo are comparing it to the libraries listed below

• dineshannayya / yifive_r0
  A 32 bit RISCV Based SOC with QSpi , Uart and 8 bit SDRAM Controller tagetted to efebless shuttle program
  ☆20Updated 2 years ago
• VUnit / cosim
  Interfacing VHDL and foreign languages with VUnit
  ☆14Updated 5 years ago
• suoto / fpga_cores
  ☆33Updated last year
• airhdl / spi-to-axi-bridge
  An SPI to AXI4-lite bridge for easy interfacing of airhdl register banks with any microcontroller.
  ☆49Updated last year
• shariethernet / RPHAX
  RPHAX provides a quick automation flow to develop and prototype hardware accelerators on Xilinx FPGAs. Currently, the framework has suppo…
  ☆18Updated 2 years ago
• tmeissner / vhdl_verification
  Examples and design pattern for VHDL verification
  ☆15Updated 9 years ago
• adki / RTL-Design-For-FPGA
  Engineering Program on RTL Design for FPGA Accelerator
  ☆29Updated 4 years ago
• freecores / ddr3_sdram
  DDR3 SDRAM controller
  ☆18Updated 10 years ago
• someone755 / ddr3-controller
  A DDR3(L) PHY and controller, written in Verilog, for Xilinx 7-Series FPGAs
  ☆68Updated 2 years ago
• alexforencich / cocotbext-uart
  UART models for cocotb
  ☆27Updated 2 years ago
• tarik-ibrahimovic / eduBOS5
  A compact, configurable RISC-V core
  ☆11Updated last month
• vsdip / vsdsram_sky130
  ☆40Updated 3 years ago
• mnasser431998 / bfu_dif_fft_rtl
  The verilog code together with cocotb testbench of BFU unit of a DIF FFT processor
  ☆14Updated 2 years ago
• tmeissner / libvhdl
  Library of reusable VHDL components
  ☆28Updated last year
• ishfaqahmed29 / SerDes
  Verilog RTL Design
  ☆34Updated 3 years ago
• www-asics-ws / wb_conmax
  WISHBONE Interconnect
  ☆11Updated 7 years ago
• ultraembedded / core_soc
  Basic Peripheral SoC (SPI, GPIO, Timer, UART)
  ☆63Updated 4 years ago
• ericgineer / CIC
  A CIC filter implemented in Verilog
  ☆22Updated 9 years ago
• olofk / wb_intercon
  Wishbone interconnect utilities
  ☆39Updated 2 months ago
• hVHDL / hVHDL_example_project
  An example project which uses many of the ideas and features of the hVHDL libraries like fixed and floating point math modules and has bu…
  ☆27Updated 3 months ago
• kmkalpana2001 / DIGITAL-VLSI-SOC-DESIGN-AND-PLANNING
  ☆28Updated last year
• Elphel / eddr3
  mirror of https://git.elphel.com/Elphel/eddr3
  ☆40Updated 7 years ago
• chili-chips-ba / openXC7-TetriSaraj
  Demo of how to use https://github.com/openXC7 tools (yosys+nextpnr-xilinx) to implement the HW side of a custom SoC with RISC-V CPU & our…
  ☆25Updated 2 months ago
• tmeissner / cryptocores
  cryptography ip-cores in vhdl / verilog
  ☆40Updated 4 years ago
• mattvenn / multi_project_tools
  tools to help make the most of the limited space we have on the Google sponsored Efabless shuttles
  ☆35Updated 2 years ago
• wallento / cocotbext-wishbone
  ☆13Updated 4 months ago
• rodrigomelo9 / FOSS-for-FPGAs
  A getting started presentation (with examples) about how to use FLOSS for FPGA development.
  ☆35Updated last year
• abdelazeem201 / ASIC-Implementation-UART
  This paper presents design of UART module for serial communication used for short-distance, low speed and exchange of data between comput…
  ☆11Updated 3 years ago
• merldsu / SAP_FPU
  This repository contains the Simple As Possible Floating Point Unit design based on the IEEE-754 Standard.
  ☆18Updated 2 years ago
• damdoy / fpga_image_processing
  IP operations in verilog (simulation and implementation on ice40)
  ☆55Updated 5 years ago