Deverne-labs / TinyML-Zybo
This repository is a collection of designs invloving FPGAs and AI technologies.
☆14Updated 2 years ago
Alternatives and similar repositories for TinyML-Zybo:
Users that are interested in TinyML-Zybo are comparing it to the libraries listed below
- A 32 bit RISCV Based SOC with QSpi , Uart and 8 bit SDRAM Controller tagetted to efebless shuttle program☆17Updated last year
- An SPI to AXI4-lite bridge for easy interfacing of airhdl register banks with any microcontroller.☆46Updated last year
- VSDBabySoC is a small mixed-signal SoC including PLL, DAC, and a RISCV-based processor named RVMYTH.☆37Updated 3 years ago
- UART models for cocotb☆26Updated last year
- A look ahead, round-robing parametrized arbiter written in Verilog.☆42Updated 4 years ago
- A compact, configurable RISC-V core☆11Updated 3 weeks ago
- Python/C/RTL cosimulation with Xilinx's xsim simulator☆65Updated 5 months ago
- Quick'n'dirty FuseSoC+cocotb example☆18Updated 2 months ago
- Basic Peripheral SoC (SPI, GPIO, Timer, UART)☆62Updated 4 years ago
- Verilog RTL Design☆31Updated 3 years ago
- The Open Source Hardware Accelerator for Efficient Neural Network Inference☆43Updated this week
- ☆40Updated 2 years ago
- Multi-Processor System on Chip verified with UVM/OSVVM/FV☆28Updated last month
- tools to help make the most of the limited space we have on the Google sponsored Efabless shuttles☆35Updated 2 years ago
- Fixed-point math library with VHDL, Python and MATLAB support☆18Updated this week
- IEEE 754 single and double precision floating point library in systemverilog and vhdl☆62Updated 2 months ago
- The verilog code together with cocotb testbench of BFU unit of a DIF FFT processor☆13Updated last year
- The open- MSP430 is an open-source 16-bit microcontroller core written in Verilog, that is compatible with the Texas Instruments MSP430 m…☆15Updated 3 years ago
- This repository contains the Simple As Possible Floating Point Unit design based on the IEEE-754 Standard.☆18Updated last year
- Wishbone interconnect utilities☆38Updated 2 weeks ago
- ☆24Updated 3 years ago
- UART -> AXI Bridge☆60Updated 3 years ago
- RISC-V soft-core PEs for TaPaSCo☆18Updated 8 months ago
- A DDR3(L) PHY and controller, written in Verilog, for Xilinx 7-Series FPGAs☆65Updated 2 years ago
- The controller is a Verilog implementation through a state machine structure per Micro datasheet specifications, and connected to a prede…☆21Updated 6 years ago
- ☆59Updated 3 years ago
- Extensible FPGA control platform☆57Updated last year
- An open source, parameterized SystemVerilog digital hardware IP library☆26Updated 8 months ago
- A simple DDR3 memory controller☆54Updated 2 years ago
- Simple RiscV core for academic purpose.☆22Updated 4 years ago