Deverne-labs / TinyML-Zybo

Related projects: ⓘ

• dineshannayya / yifive_r0
  A 32 bit RISCV Based SOC with QSpi , Uart and 8 bit SDRAM Controller tagetted to efebless shuttle program
  ☆17Updated last year
• damdoy / fpga_image_processing
  IP operations in verilog (simulation and implementation on ice40)
  ☆52Updated 4 years ago
• enclustra / en_cl_fix
  Fixed-point math library with VHDL, Python and MATLAB support
  ☆18Updated last month
• suoto / fpga_cores
  ☆32Updated last year
• AI-Vector-Accelerator / ava-core
  A lightweight core for the CV32E40 implementing the RISC-V vector extension specification. (v0.8)
  ☆29Updated 3 years ago
• PacoReinaCampo / MPSoC-DV
  Multi-Processor System on Chip verified with UVM/OSVVM/FV
  ☆25Updated this week
• someone755 / ddr3-controller
  A DDR3(L) PHY and controller, written in Verilog, for Xilinx 7-Series FPGAs
  ☆58Updated last year
• airhdl / spi-to-axi-bridge
  An SPI to AXI4-lite bridge for easy interfacing of airhdl register banks with any microcontroller.
  ☆40Updated 9 months ago
• bensampson5 / libsv
  An open source, parameterized SystemVerilog digital hardware IP library
  ☆21Updated 3 months ago
• ultraembedded / core_dbg_bridge
  UART -> AXI Bridge
  ☆52Updated 3 years ago
• Xilinx / xup_fpga_vivado_flow
  AMD Xilinx University Program Vivado tutorial
  ☆28Updated last year
• ultraembedded / core_axi_cache
  128KB AXI cache (32-bit in, 256-bit out)
  ☆39Updated 3 years ago
• AmeerAbdelhadi / 2D-Binary-Content-Addressable-Memory-BCAM
  Modular SRAM-based 2D hierarchical-search Binary Content Addressable Memory (2D-BCAM)
  ☆18Updated 9 years ago
• mnasser431998 / bfu_dif_fft_rtl
  The verilog code together with cocotb testbench of BFU unit of a DIF FFT processor
  ☆12Updated last year
• olofk / fusesocotb
  Quick'n'dirty FuseSoC+cocotb example
  ☆17Updated 3 months ago
• mattvenn / multi_project_tools
  tools to help make the most of the limited space we have on the Google sponsored Efabless shuttles
  ☆34Updated last year
• vsdip / vsdsram_sky130
  ☆35Updated 2 years ago
• ishfaqahmed29 / SerDes
  Verilog RTL Design
  ☆21Updated 3 years ago
• pulp-platform / axi_spi_slave
  ☆21Updated 3 years ago
• hVHDL / hVHDL_example_project
  An example project which uses many of the ideas and features of the hVHDL libraries like fixed and floating point math modules and has bu…
  ☆24Updated 2 months ago
• yash-k99 / vsdsram
  Design of 1024*32 (4kB) SRAM with access time < 2.5ns using OpenRAM
  ☆20Updated 4 years ago
• CESNET / ofm
  Open FPGA Modules
  ☆22Updated last week
• ultraembedded / core_soc
  Basic Peripheral SoC (SPI, GPIO, Timer, UART)
  ☆57Updated 4 years ago
• antmicro / topwrap
  A Python package for generating HDL wrappers and top modules for HDL sources
  ☆22Updated this week
• Youssefmdany / Design-and-UVM-TB-of-RISC-V-Microprocessor
  Design and UVM-TB of RISC -V Microprocessor
  ☆12Updated 2 months ago
• bmartini / verilog-arbiter
  A look ahead, round-robing parametrized arbiter written in Verilog.
  ☆40Updated 4 years ago
• spider-tronix / VLSI
  RISC V core implementation using Verilog.
  ☆23Updated 3 years ago
• shariethernet / RPHAX
  RPHAX provides a quick automation flow to develop and prototype hardware accelerators on Xilinx FPGAs. Currently, the framework has suppo…
  ☆13Updated last year
• HDLGen-ChatGPT / HDLGen-ChatGPT
  HDLGen-ChatGPT, works in tandem with ChatGPT-3.5 chat interface to enable fast digital systems design and test specification capture, and…
  ☆17Updated 3 months ago
• scale-lab / DRUM
  The Verilog source code for DRUM approximate multiplier.
  ☆26Updated last year