mchong6 / MNIST-classifier-in-SystemVerilogLinks
☆10Updated 8 years ago
Alternatives and similar repositories for MNIST-classifier-in-SystemVerilog
Users that are interested in MNIST-classifier-in-SystemVerilog are comparing it to the libraries listed below
Sorting:
- SDRAM controller with AXI4 interface☆98Updated 6 years ago
- AHB3-Lite Interconnect☆95Updated last year
- Basic Peripheral SoC (SPI, GPIO, Timer, UART)☆66Updated 5 years ago
- PCIE 5.0 Graduation project (Verification Team)☆85Updated last year
- DDR2 memory controller written in Verilog☆78Updated 13 years ago
- RTL Verilog library for various DSP modules☆91Updated 3 years ago
- A picorv32-riscv Soc with DMAC and Ethernet controller & lwip & Kirtex7@333MHz☆75Updated 4 years ago
- AXI4 and AXI4-Lite interface definitions☆96Updated 5 years ago
- This is a Multi master Multi slave compatible system bus design modeled using verilog. This is much like AMBA AHB Specification☆32Updated 5 years ago
- Interface Protocol in Verilog☆50Updated 6 years ago
- round robin arbiter☆75Updated 11 years ago
- A generic implementation of AMBA AXI4 communication protocol. The design provides a master, a slave and an interconnect with multiple mas…☆42Updated 3 years ago
- UVM实战随书源码☆55Updated 6 years ago
- AHB DMA 32 / 64 bits☆56Updated 11 years ago
- UART -> AXI Bridge☆63Updated 4 years ago
- AXI DMA 32 / 64 bits☆122Updated 11 years ago
- Fully parametrizable combinatorial parallel LFSR/CRC module☆157Updated 8 months ago
- FFT implement by verilog_测试验证已通过☆59Updated 9 years ago
- Hand written number classification done in hardware (De1-SoC board) using neural networks☆24Updated 7 years ago
- Open-source high performance AXI4-based HyperRAM memory controller☆79Updated 3 years ago
- The AHB to APB bridge is an AHB slave and the only APB master which provides an interface between the highspeed AHB and the low-power APB…☆67Updated 3 years ago
- Advanced encryption standard (AES128, AES192, AES256) Encryption and Decryption Implementation in Verilog HDL☆120Updated 3 years ago
- AMBA bus generator including AXI, AHB, and APB☆107Updated 4 years ago
- ☆69Updated 9 years ago
- Verilog SPI master and slave☆60Updated 9 years ago
- Verilog UART☆184Updated 12 years ago
- A simple implementation of a UART modem in Verilog.☆160Updated 3 years ago
- Title : Communication Bridge between I2C and SPI Platform : RTL Coding (Verilog/System Verilog/VHDL) Duration : 1 Month Description : Bot…☆19Updated 7 years ago
- A simple DDR3 memory controller☆60Updated 2 years ago
- Fixed Point Math Library for Verilog☆143Updated 11 years ago