mchong6 / MNIST-classifier-in-SystemVerilogLinks
☆10Updated 7 years ago
Alternatives and similar repositories for MNIST-classifier-in-SystemVerilog
Users that are interested in MNIST-classifier-in-SystemVerilog are comparing it to the libraries listed below
Sorting:
- SDRAM controller with AXI4 interface☆94Updated 5 years ago
- Interface Protocol in Verilog☆50Updated 5 years ago
- RTL Verilog library for various DSP modules☆88Updated 3 years ago
- DDR2 memory controller written in Verilog☆78Updated 13 years ago
- A set of Wishbone Controlled SPI Flash Controllers☆82Updated 2 years ago
- Hand written number classification done in hardware (De1-SoC board) using neural networks☆24Updated 7 years ago
- Verilog modules required to get the OV7670 camera working☆73Updated 6 years ago
- This XUP course provides an introduction to embedded system design on Zynq using the Xilinx Vivado software suite.☆84Updated last year
- AHB3-Lite Interconnect☆89Updated last year
- Basic Peripheral SoC (SPI, GPIO, Timer, UART)☆64Updated 5 years ago
- 16-bit Adder Multiplier hardware on Digilent Basys 3☆75Updated last year
- AHB DMA 32 / 64 bits☆55Updated 10 years ago
- Open-source high performance AXI4-based HyperRAM memory controller☆75Updated 2 years ago
- IP operations in verilog (simulation and implementation on ice40)☆55Updated 5 years ago
- round robin arbiter☆74Updated 10 years ago
- 32-Bit Algorithms of Floating Point Operations are implemented on Verilog with logic Operations.☆85Updated 6 years ago
- A 16-point radix-4 FFT chip, including Verilog codes, netlists and layout. Group project.☆64Updated 9 months ago
- ☆36Updated 9 years ago
- Verilog SPI master and slave☆54Updated 9 years ago
- AXI DMA 32 / 64 bits☆114Updated 10 years ago
- A look ahead, round-robing parametrized arbiter written in Verilog.☆42Updated 5 years ago
- AXI4 BFM in Verilog☆32Updated 8 years ago
- AMBA bus generator including AXI, AHB, and APB☆101Updated 3 years ago
- AXI4 and AXI4-Lite interface definitions☆93Updated 4 years ago
- HDL code for a DDR4 memory controller implementing an Open Page Policy and Out of Order execution.☆74Updated 7 years ago
- Real-time streaming of OV7670 camera via VGA with a 640x480 resolution at 30fps☆62Updated 3 years ago
- SystemVerilog HDL and TB code Deep Neural Network Hardware Accelerator implementation on zybo 7010 FPGA and also C code for Vivado SDK So…☆110Updated 5 years ago
- This is a Multi master Multi slave compatible system bus design modeled using verilog. This is much like AMBA AHB Specification☆32Updated 5 years ago
- A simple DDR3 memory controller☆55Updated 2 years ago
- A DDR3(L) PHY and controller, written in Verilog, for Xilinx 7-Series FPGAs☆71Updated 2 years ago