Intelligent-Microsystems-Lab / SNNQuantPrune
Code for the ISCAS23 paper "The Hardware Impact of Quantization and Pruning for Weights in Spiking Neural Networks"
☆11Updated 2 years ago
Alternatives and similar repositories for SNNQuantPrune:
Users that are interested in SNNQuantPrune are comparing it to the libraries listed below
- A three-layer LIF neuron SNN accelerator. The first layer is the input layer and has 784 neurons, that receive the encoded spikes. The se…☆11Updated last year
- CORDIC-SNN, followed with "Unsupervised learning of digital recognition using STDP" published in 2015, frontiers☆23Updated 5 years ago
- The CyNAPSE Neuromorphic Accelerator: A Digital Spiking neural network accelerator written in fully synthesizable verilog HDL☆33Updated 5 years ago
- ☆18Updated 4 years ago
- Hardware implementation of Spiking Neural Network on a PYNQ-Z1 board☆36Updated 5 years ago
- Models and training scripts for "LSTMs for Keyword Spotting with ReRAM-based Compute-In-Memory Architectures" (ISCAS 2021).☆14Updated 4 years ago
- ☆17Updated 4 years ago
- Framework for radix encoded SNN on FPGA☆12Updated 3 years ago
- ☆16Updated 11 months ago
- The project includes SRAM In Memory Computing Accelerator with updates in design/circuits submitted previously in MPW7, by IITD researche…☆11Updated 2 years ago
- ☆24Updated 2 years ago
- Leaky Integrate and Fire (LIF) model implementation for FPGA☆60Updated last year
- A Spiking Neuron Network Project in Verilog Implementation☆21Updated 7 years ago
- Benchmark framework of compute-in-memory based accelerators for deep neural network (on-chip training chip focused)☆48Updated 3 years ago
- Spiking neural network implementation using Verilog with LIF (Leaky Integrate-and-Fire) neurons☆15Updated 4 years ago
- [FPL 2021] SyncNN: Evaluating and Accelerating Spiking Neural Networks on FPGAs.☆55Updated 3 years ago
- I will share some useful or interesting papers about neuromorphic processor☆24Updated 2 months ago
- ☆46Updated last year
- tinyODIN digital spiking neural network (SNN) processor - HDL source code and documentation.☆56Updated 2 years ago
- IEEE Transactions on Circuits and Systems I: Efficient FPGA Implementations of Pair and Triplet-based STDP for Neuromorphic Architectures☆26Updated 5 years ago
- FPGA acceleration of a Spike-Timing-Dependent Plasticity learning algorithm for Spiking Neural Networks☆35Updated 4 years ago
- Spiking Neural Network RTL Implementation☆55Updated 3 years ago
- A Custom RISC-V Instruction Extension for SNN and CNN Computation☆13Updated 8 months ago
- MINT, Multiplier-less INTeger Quantization for Energy Efficient Spiking Neural Networks, ASP-DAC 2024, Nominated for Best Paper Award☆13Updated last year
- SATA_Sim is an energy estimation framework for Backpropagation-Through-Time (BPTT) based Spiking Neural Networks (SNNs) training and infe…☆26Updated 7 months ago
- ReRAM implementation on CNN☆18Updated 6 years ago
- A nest brain simulator based on FPGA(LIF NEURON)☆14Updated 3 years ago
- Hardware and software implementation of Sparsely-active SNNs☆14Updated 3 months ago
- ReckOn: A Spiking RNN Processor Enabling On-Chip Learning over Second-Long Timescales - HDL source code and documentation.☆84Updated 3 years ago
- LoAS: Fully Temporal-Parallel Dataflow for Dual-Sparse Spiking Neural Networks, MICRO 2024.☆10Updated last month