A project dedicated to developing a hardware Integrated Circuit (IC) for a Spike Neural Network (SNN), powered by the RTL code generated by ChatGPT-4 with advanced optimizations.
☆66Feb 18, 2024Updated 2 years ago
Alternatives and similar repositories for edabk_brain_soc
Users that are interested in edabk_brain_soc are comparing it to the libraries listed below
Sorting:
- The project includes SRAM In Memory Computing Accelerator with updates in design/circuits submitted previously in MPW7, by IITD researche…☆16Jan 6, 2023Updated 3 years ago
- CORDIC-SNN, followed with "Unsupervised learning of digital recognition using STDP" published in 2015, frontiers☆25Feb 9, 2020Updated 6 years ago
- A three-layer LIF neuron SNN accelerator. The first layer is the input layer and has 784 neurons, that receive the encoded spikes. The se…☆15Sep 9, 2023Updated 2 years ago
- A Spiking Neuron Network Project in Verilog Implementation☆26Apr 5, 2018Updated 7 years ago
- tinyODIN digital spiking neural network (SNN) processor - HDL source code and documentation.☆75Mar 30, 2023Updated 2 years ago
- FPGA Design of a Spiking Neural Network.☆46May 15, 2024Updated last year
- FPGA acceleration of a Spike-Timing-Dependent Plasticity learning algorithm for Spiking Neural Networks☆40Jun 29, 2020Updated 5 years ago
- ODIN online-learning digital spiking neural network (SNN) processor - HDL source code and documentation.☆220Apr 20, 2019Updated 6 years ago
- [TVLSI'23] This repository contains the source code for the paper "FireFly: A High-Throughput Hardware Accelerator for Spiking Neural Net…☆24Apr 4, 2024Updated last year
- [TCAD'24] This repository contains the source code for the paper "FireFly v2: Advancing Hardware Support for High-Performance Spiking Neu…☆23May 9, 2024Updated last year
- ReckOn: A Spiking RNN Processor Enabling On-Chip Learning over Second-Long Timescales - HDL source code and documentation.☆92Feb 18, 2022Updated 4 years ago
- Energy-efficient Event-driven Spiking Neural Network accelerator for FPGA with PyTorch integration☆113Feb 10, 2026Updated 3 weeks ago
- Router 1 x 3 verilog implementation☆15Sep 5, 2021Updated 4 years ago
- SNN on FPGA☆12Apr 26, 2022Updated 3 years ago
- Fully opensource spiking neural network accelerator☆168Feb 13, 2023Updated 3 years ago
- ☆30Jun 8, 2022Updated 3 years ago
- TIDENet is an ASIC written in Verilog for Tiny Image Detection at Edge with neural networks (TIDENet) using DNNWeaver 2.0, the Google Sky…☆17Jan 30, 2023Updated 3 years ago
- Spiking neural network inference engine for 7-Series FPGAs☆26Aug 31, 2025Updated 6 months ago
- VietConizer: Vietnamese OCR with NVIDIA DALI☆16Jul 5, 2025Updated 8 months ago
- The CyNAPSE Neuromorphic Accelerator: A Digital Spiking neural network accelerator written in fully synthesizable verilog HDL☆37Sep 25, 2019Updated 6 years ago
- ☆20Apr 7, 2021Updated 4 years ago
- Repository collecting papers about neuromorphic hardware, such as ASIC and FPGA implementations of SNNs and stuff.☆205Nov 4, 2023Updated 2 years ago
- HedgeHog Fused Spiking Neural Network Emulator/Compute Engine is a hardware implementation of a SNN designed for implementation in Xilinx…☆60Feb 10, 2026Updated 3 weeks ago
- [FPL 2021] SyncNN: Evaluating and Accelerating Spiking Neural Networks on FPGAs.☆64Jul 28, 2021Updated 4 years ago
- Hardware implementation of Spiking Neural Network on a PYNQ-Z1 board☆39Jun 14, 2019Updated 6 years ago
- A simple from scratch implementation of a Spiking-Neural-Network with STDP in Python which is beeing trained on MNIST.☆47Aug 30, 2024Updated last year
- This repository presents the mixed signal design of a Counter Type/ Ramp Type ADC. The Digital part of the circuit i.e 4- bit counter is …☆11May 2, 2022Updated 3 years ago
- EE4415 Project : AES Verilog☆10Apr 25, 2019Updated 6 years ago
- This is the Google/EFabless/Skywater Caravel submission of an Analog Spiking Neuron Circuit. The submission also includes a SONOS transis…☆12Apr 21, 2023Updated 2 years ago
- Neuromorphic ASIC with 96 neurons on Tiny Tapeout 7☆11May 25, 2024Updated last year
- Working 8x8 systolic array hardware implemented in Xilinx Vivado, operated and controlled in software using Xilinx Vitis☆15Feb 16, 2024Updated 2 years ago
- IEEE Transactions on Circuits and Systems I: Efficient FPGA Implementations of Pair and Triplet-based STDP for Neuromorphic Architectures☆29Jul 7, 2019Updated 6 years ago
- ☆56Jan 29, 2024Updated 2 years ago
- A nest brain simulator based on FPGA(LIF NEURON)☆15Dec 14, 2021Updated 4 years ago
- An FPGA design for simulating biological neurons☆17Jul 5, 2024Updated last year
- ☆12Dec 22, 2020Updated 5 years ago
- ☆13May 10, 2018Updated 7 years ago
- Here is the official code for ICASSP 2024 "Optimal ANN-SNN Conversion with Group Neurons".☆14Mar 1, 2024Updated 2 years ago
- SATA_Sim is an energy estimation framework for Backpropagation-Through-Time (BPTT) based Spiking Neural Networks (SNNs) training and infe…☆28Sep 23, 2024Updated last year