coreylammie / TCAS-STDP
IEEE Transactions on Circuits and Systems I: Efficient FPGA Implementations of Pair and Triplet-based STDP for Neuromorphic Architectures
☆26Updated 5 years ago
Alternatives and similar repositories for TCAS-STDP:
Users that are interested in TCAS-STDP are comparing it to the libraries listed below
- The CyNAPSE Neuromorphic Accelerator: A Digital Spiking neural network accelerator written in fully synthesizable verilog HDL☆33Updated 5 years ago
- FPGA acceleration of a Spike-Timing-Dependent Plasticity learning algorithm for Spiking Neural Networks☆35Updated 4 years ago
- Spiking Neural Network RTL Implementation☆55Updated 3 years ago
- HedgeHog Fused Spiking Neural Network Emulator/Compute Engine is a hardware implementation of a SNN designed for implementation in Xilinx…☆58Updated last month
- A repository FPGA-friendly SNN models☆32Updated 4 years ago
- ReckOn: A Spiking RNN Processor Enabling On-Chip Learning over Second-Long Timescales - HDL source code and documentation.☆84Updated 3 years ago
- [FPL 2021] SyncNN: Evaluating and Accelerating Spiking Neural Networks on FPGAs.☆55Updated 3 years ago
- CORDIC-SNN, followed with "Unsupervised learning of digital recognition using STDP" published in 2015, frontiers☆23Updated 5 years ago
- Hardware implementation of Spiking Neural Network on a PYNQ-Z1 board☆36Updated 5 years ago
- tinyODIN digital spiking neural network (SNN) processor - HDL source code and documentation.☆55Updated 2 years ago
- ☆17Updated 4 years ago
- Leaky Integrate and Fire (LIF) model implementation for FPGA☆60Updated last year
- ☆24Updated 2 years ago
- ☆17Updated 4 years ago
- Spiking neural network for Zynq devices with Vivado HLS☆33Updated 7 years ago
- A Spiking neural network simulator NEST base on FPGA‘s cluster（LIF NEURON）☆17Updated 5 years ago
- A Spiking Neuron Network Project in Verilog Implementation☆21Updated 7 years ago
- A three-layer LIF neuron SNN accelerator. The first layer is the input layer and has 784 neurons, that receive the encoded spikes. The se…☆11Updated last year
- FPGA Design of a Spiking Neural Network.☆38Updated 11 months ago
- Framework for radix encoded SNN on FPGA☆12Updated 3 years ago
- Spiking neural network implementation using Verilog with LIF (Leaky Integrate-and-Fire) neurons☆15Updated 4 years ago
- A nest brain simulator based on FPGA(LIF NEURON)☆14Updated 3 years ago
- Code for the ISCAS23 paper "The Hardware Impact of Quantization and Pruning for Weights in Spiking Neural Networks"☆11Updated last year
- ☆18Updated 2 years ago
- ☆46Updated last year
- This is the RTL implementation of Shenjing, a low power neuromorphic computing accelerator☆17Updated 5 years ago
- ODIN online-learning digital spiking neural network (SNN) processor - HDL source code and documentation.☆182Updated 5 years ago
- Notebooks for Hardware-Aware Training of Spiking Neural Networks. Open-Source Neuromorphic Circuit Design Tutorial at ESSCIRC 2023.☆23Updated last year
- Notebooks and code for Neuromorphic Hardware Workshop at ISFPGA 2024.☆46Updated last year
- I will share some useful or interesting papers about neuromorphic processor☆24Updated 2 months ago