ChFrenkel / ODIN
ODIN online-learning digital spiking neural network (SNN) processor - HDL source code and documentation.
☆152Updated 5 years ago
Related projects: ⓘ
- ReckOn: A Spiking RNN Processor Enabling On-Chip Learning over Second-Long Timescales - HDL source code and documentation.☆71Updated 2 years ago
- FPGA acceleration of a Spike-Timing-Dependent Plasticity learning algorithm for Spiking Neural Networks☆33Updated 4 years ago
- CORDIC-SNN, followed with "Unsupervised learning of digital recognition using STDP" published in 2015, frontiers☆19Updated 4 years ago
- Spiking Neural Network RTL Implementation☆41Updated 3 years ago
- A repository FPGA-friendly SNN models☆27Updated 3 years ago
- ☆12Updated this week
- A Spiking Neuron Network Project in Verilog Implementation☆16Updated 6 years ago
- HedgeHog Fused Spiking Neural Network Emulator/Compute Engine is a hardware implementation of a SNN designed for implementation in Xilinx…☆50Updated last year
- The CyNAPSE Neuromorphic Accelerator: A Digital Spiking neural network accelerator written in fully synthesizable verilog HDL☆30Updated 4 years ago
- tinyODIN digital spiking neural network (SNN) processor - HDL source code and documentation.☆34Updated last year
- ☆81Updated 4 years ago
- Repository collecting papers about neuromorphic hardware, such as ASIC and FPGA implementations of SNNs and stuff.☆133Updated 10 months ago
- [FPL 2021] SyncNN: Evaluating and Accelerating Spiking Neural Networks on FPGAs.☆50Updated 3 years ago
- ☆12Updated 3 years ago
- Leaky Integrate and Fire (LIF) model implementation for FPGA☆39Updated 10 months ago
- Hardware implementation of Spiking Neural Network on a PYNQ-Z1 board☆28Updated 5 years ago
- A three-layer LIF neuron SNN accelerator. The first layer is the input layer and has 784 neurons, that receive the encoded spikes. The se…☆9Updated last year
- A Spiking neural network simulator NEST base on FPGA‘s cluster(LIF NEURON)☆17Updated 4 years ago
- This repository hosts the code for an FPGA based accelerator for convolutional neural networks☆114Updated 3 months ago
- IEEE Transactions on Circuits and Systems I: Efficient FPGA Implementations of Pair and Triplet-based STDP for Neuromorphic Architectures☆22Updated 5 years ago
- A project dedicated to developing a hardware Integrated Circuit (IC) for a Spike Neural Network (SNN), powered by the RTL code generated …☆34Updated 7 months ago
- ☆39Updated 7 months ago
- A nest brain simulator based on FPGA(LIF NEURON)☆13Updated 2 years ago
- FPGA Design of a Spiking Neural Network.☆30Updated 4 months ago
- Fully opensource spiking neural network accelerator☆119Updated last year
- A SystemVerilog implementation of Row-Stationary dataflow and Hierarchical Mesh Network-on-Chip Architecture based on Eyeriss CNN Acceler…☆121Updated 4 years ago
- ☆16Updated 3 years ago
- ☆21Updated 2 years ago
- Spiking neural network implementation using Verilog with LIF (Leaky Integrate-and-Fire) neurons☆10Updated 4 years ago
- Convolutional Neural Network RTL-level Design☆25Updated 2 years ago