ChFrenkel / ODIN
ODIN online-learning digital spiking neural network (SNN) processor - HDL source code and documentation.
☆182Updated 6 years ago
Alternatives and similar repositories for ODIN:
Users that are interested in ODIN are comparing it to the libraries listed below
- tinyODIN digital spiking neural network (SNN) processor - HDL source code and documentation.☆56Updated 2 years ago
- Spiking Neural Network RTL Implementation☆56Updated 3 years ago
- HedgeHog Fused Spiking Neural Network Emulator/Compute Engine is a hardware implementation of a SNN designed for implementation in Xilinx…☆58Updated 2 months ago
- FPGA acceleration of a Spike-Timing-Dependent Plasticity learning algorithm for Spiking Neural Networks☆35Updated 4 years ago
- A repository FPGA-friendly SNN models☆34Updated 4 years ago
- ReckOn: A Spiking RNN Processor Enabling On-Chip Learning over Second-Long Timescales - HDL source code and documentation.☆84Updated 3 years ago
- ☆89Updated 5 years ago
- CORDIC-SNN, followed with "Unsupervised learning of digital recognition using STDP" published in 2015, frontiers☆23Updated 5 years ago
- Leaky Integrate and Fire (LIF) model implementation for FPGA☆62Updated last year
- The CyNAPSE Neuromorphic Accelerator: A Digital Spiking neural network accelerator written in fully synthesizable verilog HDL☆33Updated 5 years ago
- A Spiking Neuron Network Project in Verilog Implementation☆22Updated 7 years ago
- [FPL 2021] SyncNN: Evaluating and Accelerating Spiking Neural Networks on FPGAs.☆55Updated 3 years ago
- Repository collecting papers about neuromorphic hardware, such as ASIC and FPGA implementations of SNNs and stuff.☆160Updated last year
- This repository hosts the code for an FPGA based accelerator for convolutional neural networks☆150Updated 10 months ago
- Hardware implementation of Spiking Neural Network on a PYNQ-Z1 board☆36Updated 5 years ago
- A SystemVerilog implementation of Row-Stationary dataflow and Hierarchical Mesh Network-on-Chip Architecture based on Eyeriss CNN Acceler…☆157Updated 5 years ago
- Fully opensource spiking neural network accelerator☆143Updated 2 years ago
- FPGA Design of a Spiking Neural Network.☆39Updated 11 months ago
- IEEE Transactions on Circuits and Systems I: Efficient FPGA Implementations of Pair and Triplet-based STDP for Neuromorphic Architectures☆26Updated 5 years ago
- A Spiking neural network simulator NEST base on FPGA‘s cluster（LIF NEURON）☆17Updated 5 years ago
- Spiking neural network implementation using Verilog with LIF (Leaky Integrate-and-Fire) neurons☆15Updated 4 years ago
- IC implementation of Systolic Array for TPU☆232Updated 6 months ago
- Convolutional accelerator kernel, target ASIC & FPGA☆196Updated 2 years ago
- This project aims to develop a novel neuromorphic NoC architecture based on RISC-V ISA to support spiking neural network applications, an…☆21Updated last year
- This is a fully parameterized verilog implementation of computation kernels for accleration of the Inference of Convolutional Neural Netw…☆177Updated last year
- ☆18Updated 4 years ago
- ☆108Updated 4 years ago
- Convolutional Neural Network Using High Level Synthesis☆87Updated 4 years ago
- 清華大學 | 積體電路設計實驗 (IC LAB) | 110上☆36Updated 2 years ago
- An LeNet RTL implement onto FPGA☆46Updated 7 years ago