ribesstefano / Mapping-Multiple-LSTM-Models-on-FPGAsLinks
Includes the SVD-based approximation algorithms for compressing deep learning models and the FPGA accelerators exploiting such approximation mechanism, as described in the paper Mapping multiple LSTM models on FPGAs.
☆15Updated 2 years ago
Alternatives and similar repositories for Mapping-Multiple-LSTM-Models-on-FPGAs
Users that are interested in Mapping-Multiple-LSTM-Models-on-FPGAs are comparing it to the libraries listed below
Sorting:
- SSR: Spatial Sequential Hybrid Architecture for Latency Throughput Tradeoff in Transformer Acceleration (Full Paper Accepted in FPGA'24)☆32Updated this week
- An FPGA Accelerator for Transformer Inference☆85Updated 3 years ago
- ☆16Updated 4 years ago
- [TRETS'23, FPT'20] CHIP-KNN: Configurable and HIgh-Performance K-Nearest Neighbors Accelerator on Cloud FPGAs☆18Updated last year
- FPGA-based hardware accelerator for Vision Transformer (ViT), with Hybrid-Grained Pipeline.☆75Updated 5 months ago
- [ASAP 2020; FPGA 2020] Hardware architecture to accelerate GNNs (common IP modules for minibatch training and full batch inference)☆41Updated 4 years ago
- An Automated Framework for Generic Graph Neural Network Accelerator Generation, Simulation, and Optimization☆23Updated 8 months ago
- Linux docker for the DNN accelerator exploration infrastructure composed of Accelergy and Timeloop☆54Updated 3 months ago
- A Reconfigurable Accelerator with Data Reordering Support for Low-Cost On-Chip Dataflow Switching☆55Updated 3 months ago
- Implementation of paper "GraphACT: Accelerating GCN Training on CPU-FPGA Heterogeneous Platform".☆10Updated 5 years ago
- A Unified Framework for Training, Mapping and Simulation of ReRAM-Based Convolutional Neural Network Acceleration☆34Updated 3 years ago
- An HLS based winograd systolic CNN accelerator☆53Updated 3 years ago
- ☆17Updated 10 months ago
- ☆65Updated 5 months ago
- An end-to-end GCN inference accelerator written in HLS☆19Updated 3 years ago
- Systolic array implementations for Cholesky, LU, and QR decomposition☆43Updated 8 months ago
- A systolic array simulator for multi-cycle MACs and varying-byte words, with the paper accepted to HPCA 2022.☆79Updated 3 years ago
- A general framework for optimizing DNN dataflow on systolic array☆39Updated 4 years ago
- Collection of kernel accelerators optimised for LLM execution☆19Updated 3 months ago
- ☆49Updated 3 years ago
- High-Performance Sparse Linear Algebra on HBM-Equipped FPGAs Using HLS☆93Updated 9 months ago
- [TCAD'23] AccelTran: A Sparsity-Aware Accelerator for Transformers☆49Updated last year
- ☆27Updated 3 months ago
- HLSFactory: A Framework Empowering High-Level Synthesis Datasets for Machine Learning and Beyond☆38Updated this week
- A dataflow architecture for universal graph neural network inference via multi-queue streaming.☆73Updated 2 years ago
- An FPGA accelerator for general-purpose Sparse-Matrix Dense-Matrix Multiplication (SpMM).☆81Updated 11 months ago
- RTL generator for SpGEMM☆12Updated 4 years ago
- FracBNN: Accurate and FPGA-Efficient Binary Neural Networks with Fractional Activations☆94Updated 3 years ago
- Simulator for LLM inference on an abstract 3D AIMC-based accelerator☆19Updated 2 months ago
- ☆61Updated last month