elchatz / IntTrapsLinks
400 nm SiO2 capacitor simulation of interface trap formation with state transitions in Sentaurus TCAD
☆12Updated 8 years ago
Alternatives and similar repositories for IntTraps
Users that are interested in IntTraps are comparing it to the libraries listed below
Sorting:
- Repository that provide a wrapper to use the software TCAD Sentaurus with Python.☆52Updated last year
- Two Stage CMOS Operational Amplifier IP Design using Skywater 130nm Technology☆22Updated 3 years ago
- ☆12Updated 3 years ago
- Advanced integrated circuits 2023☆32Updated last year
- TCAD Semiconductor Device Simulator☆230Updated last month
- Open-source version of the Genius Semiconductor Device Simulator☆152Updated 5 years ago
- This project shows the design of a frequency synthesizer PLL system that produces a 1.92 GHz signal with a reference input of 30 MHz, wit…☆78Updated 2 years ago
- A python framework for EDA applications.☆37Updated 14 years ago
- Suprem4 Semiconductor Process Simulator of Stanford Univ.☆38Updated 11 years ago
- Comprehensive numerical modeling of filamentary RRAM devices including voltage ramp-rate and cycle-to-cycle variations☆24Updated last year
- A simple but powerful Python package for creating photolithography masks in the GDSII format.☆95Updated 2 years ago
- This project discusses the design of an 8-bit asynchronous successive approximation register (SAR) analog-to-digital converter (ADC) impl…☆184Updated last year
- COCOA: Collaborative Compendium on Analog Integrated Circuits☆20Updated 3 months ago
- Time to Digital Converter on an FPGA☆14Updated 5 years ago
- ☆83Updated 10 months ago
- This project shows how to design a clock bootstrapped circuit to improve the nonlinearity of the switch used in Track & Hold circuit. A c…☆12Updated 6 years ago
- Simple 3D layout viewer for KLayout (Salt package)☆20Updated 6 years ago
- Cadence SKILL utilities that have boosted my productivity considerably for 10+ years.☆51Updated last week
- Verilog-A simulation models☆89Updated last month
- The project is about building an 8-row by 8-bit 6T SRAM memory array, & a 3-to-8 decoder that's used to access the SRAM array. The layout…☆81Updated 3 years ago
- Files associated with Digital Integrated Circuits (ecen4303) at Oklahoma State University☆10Updated last year
- Python port of Prof. Boris Murmann's gm/ID Starter Kit☆54Updated 8 years ago
- Python script to convert image files to GDSII files☆67Updated 9 months ago
- Verilog implementation of a tapped delay line TDC☆44Updated 7 years ago
- Generic Process Design Kit for Gdsfactory☆20Updated last year
- This project is about designing a 1.5 bit stage Pipeline ADC & the OpAmp required for its MDAC.☆36Updated 3 years ago
- Parametric layout generator for digital, analog and mixed-signal integrated circuits☆63Updated this week
- Python library for SerDes modelling☆74Updated last year
- EE 628: Analysis and Design of Integrated Circuits (University of Hawaiʻi at Mānoa)☆169Updated 3 months ago
- A python3 gm/ID starter kit☆56Updated 3 months ago