Alternatives and similar repositories for IntTraps

Users that are interested in IntTraps are comparing it to the libraries listed below

• thomashirtz / pytaurus
  Repository that provide a wrapper to use the software TCAD Sentaurus with Python.
  ☆49Updated 11 months ago
• cogenda / Suprem4
  Suprem4 Semiconductor Process Simulator of Stanford Univ.
  ☆36Updated 10 years ago
• kadomoto / picture-to-gds
  Python script to convert image files to GDSII files
  ☆63Updated 4 months ago
• LGG1997 / FPGA_TDC_1_0
  ☆11Updated 2 years ago
• zwh42 / KLayout-PyMacros
  Python library for KLayout (https://www.klayout.de/)
  ☆1Updated 5 years ago
• zhujialin2018 / mumax3-STT-SOT
  mumax3 with sot(spin orbit torque)
  ☆10Updated 2 years ago
• MK8J / semiconductor
  a place for semiconductor models
  ☆14Updated 7 years ago
• rohinthram / avsd_opamp
  Two Stage CMOS Operational Amplifier IP Design using Skywater 130nm Technology
  ☆20Updated 2 years ago
• DipeshNiraula / RRAM-COMSOL-Model
  Comprehensive numerical modeling of filamentary RRAM devices including voltage ramp-rate and cycle-to-cycle variations
  ☆21Updated last year
• bosho86 / BallisticMobility
  Ballistic Mobility PMIs inside of Sentaurus S-Device
  ☆10Updated 5 years ago
• quartiq / redpid
  migen + misoc + redpitaya = digital servo
  ☆40Updated 6 years ago
• cogenda / Genius-TCAD-Open
  Open-source version of the Genius Semiconductor Device Simulator
  ☆142Updated 5 years ago
• red435 / verilog_APB_SPI_interface
  SPI interface connect to APB BUS with Verilog HDL
  ☆32Updated 4 years ago
• cogenda / pyEDA
  A python framework for EDA applications.
  ☆34Updated 14 years ago
• gdsfactory / ubc
  UBC Siepic Ebeam PDK from edx course
  ☆28Updated 2 months ago
• aisichenko / gdsfactory-workshop-ucsb
  ☆10Updated last year
• praveenkhemalapure / DDR3-controller-verification
  DDR3 function verification environment in UVM
  ☆25Updated 7 years ago
• charkster / spi_slave_verilog
  SPI bus slave and flip-flop register memory map implemented in Verilog 2001 for FPGAs
  ☆16Updated 5 years ago
• ulfgri / gdsii-toolbox
  Octave and MATLAB toolbox for GDSII stream format
  ☆69Updated 4 years ago
• visky2096 / AHB-to-I2C
  Attempt to setup a bridge between AHB and I2C by constructing dedicated modules of AHB master , AHB slave , APB master , APB slave, I2C m…
  ☆22Updated 6 years ago
• deekshithkrishnegowda / AHB2APB-bridge-IP-core-verification
  Maven Silicon Project
  ☆19Updated 6 years ago
• mdecea / power_handling_Si_resonators
  Code implementing the system of nonlinear equations that describes nonlinearities in silicon microring modulators.
  ☆10Updated 4 years ago
• devsim / devsim
  TCAD Semiconductor Device Simulator
  ☆201Updated 6 months ago
• muhammadaldacher / Analog-Design-of-Bootstrapped-Switch
  This project shows how to design a clock bootstrapped circuit to improve the nonlinearity of the switch used in Track & Hold circuit. A c…
  ☆11Updated 5 years ago
• shinde-shantanu / FPGA_TDC
  Time to Digital Converter on an FPGA
  ☆14Updated 4 years ago
• hanysalah / uart2bustestbench
  UVM Verification IP to uart2bus IP.
  ☆22Updated 3 years ago
• ishfaqahmed29 / SerDes
  Verilog RTL Design
  ☆40Updated 3 years ago
• richard259 / serdespy
  Python library for SerDes modelling
  ☆70Updated 11 months ago
• PranavGovekar / tdcOnFPGA
  Implementation of tappped delay line TDC on FPGA
  ☆12Updated 2 years ago
• Shashi18 / I2C-Verilog
  Verilog Code for I2C Protocol
  ☆18Updated 4 years ago