Shashi18 / I2C-VerilogLinks
Verilog Code for I2C Protocol
☆20Updated 4 years ago
Alternatives and similar repositories for I2C-Verilog
Users that are interested in I2C-Verilog are comparing it to the libraries listed below
Sorting:
- ☆47Updated 4 years ago
- System Verilog using Functional Verification☆12Updated last year
- Maven Silicon project - AHB-to-APB Bridge Verification using UVM Methodology.☆95Updated 2 years ago
- Architectural design of data router in verilog☆31Updated 5 years ago
- Asynchronous fifo in verilog☆35Updated 9 years ago
- PCIE 5.0 Graduation project (Verification Team)☆78Updated last year
- A repository aggregating links to essential documentation, tutorials, and research papers for hardware Design Verification.☆20Updated 2 months ago
- The AHB to APB bridge is an AHB slave and the only APB master which provides an interface between the highspeed AHB and the low-power APB…☆63Updated 2 years ago
- Comprehensive verification suite for the AHB2APB Bridge design, featuring SystemVerilog and UVM-based methodologies. 🌉🚀☆31Updated last year
- I am a VLSI enthusiast and I'm going to start my journey of 100 days of RTL.☆23Updated 2 years ago
- UVM based Verification of SPI_Protocol. A Serial intra System Communication Peripheral Protocol.☆10Updated last year
- DDR2 memory controller written in Verilog☆77Updated 13 years ago
- Developed with the aim of providing engineers and designers with a centralized resource, this repository serves as a valuable reference f…☆61Updated last year
- Verification IP for APB protocol☆68Updated 4 years ago
- ☆10Updated last year
- Presents a verification use case for a typical Asynchronous FIFO based on Systemverilog and UVM.☆54Updated 5 years ago
- SystemVerilog examples and projects☆18Updated 2 months ago
- UVM Testbench to verify serial transmission of data between SPI master and slave☆48Updated 5 years ago
- AXI Interconnect☆51Updated 3 years ago
- Designing means to communicate as an SPI master, being a part of AXI interface☆17Updated last year
- In this tutorial, you learn how to implement a design from RTL-to-GDSII using Cadence® tools.☆70Updated last year
- ☆16Updated last year
- This asynchrounous FIFO deisgn and UVM verificaiton is one case study of me. The design is based on Cliff Cumming's paper and the UVM is…☆64Updated last year
- Static Timing Analysis Full Course☆57Updated 2 years ago
- This Repo contains Codes of RTLs for implementation of various circuit designs using Verilog in Xilinx ISE 14.7 and sometimes Modelsim to…☆19Updated 2 years ago
- Advanced encryption standard (AES) algorithm has been widely deployed in cryptographic applications. This work proposes a low power and h…☆22Updated 4 years ago
- Master and Slave made using AMBA AXI4 Lite protocol.☆26Updated 4 years ago
- SPI interface connect to APB BUS with Verilog HDL☆35Updated 4 years ago
- Examples and reference for System Verilog Assertions☆86Updated 8 years ago
- 5 Day TCL begginer to advanced training workshop by VSD☆18Updated last year