raiyyanfaisal09 / AHB_APB-RTL
AHB-APB Bridge RTL Design
☆16Updated 7 years ago
Alternatives and similar repositories for AHB_APB-RTL
Users that are interested in AHB_APB-RTL are comparing it to the libraries listed below
Sorting:
- ☆13Updated 4 years ago
- Maven Silicon project - AHB-to-APB Bridge Verification using UVM Methodology.☆88Updated last year
- The AHB to APB bridge is an AHB slave and the only APB master which provides an interface between the highspeed AHB and the low-power APB…☆58Updated 2 years ago
- Based on ARM AMBA bus protocol, Verilog is used to design the digital circuit.☆122Updated 4 years ago
- Verification IP for APB protocol☆64Updated 4 years ago
- ☆36Updated 9 years ago
- Master and Slave made using AMBA AXI4 Lite protocol.☆26Updated 4 years ago
- AHB to APB Bridge VIP☆29Updated 6 years ago
- VIP for AXI Protocol☆134Updated 2 years ago
- AXI Interconnect☆49Updated 3 years ago
- yet another AXI testbench repo. ;) This is for my UVM practice. https://marcoz001.github.io/axi-uvm/☆115Updated 7 years ago
- An uvm verification env for ahb2apb bridge☆50Updated 4 years ago
- AXI master to AHB slave, support INCR/WRAP, out of standing, do not advanced feature such as support out of order, retry, split, etc☆41Updated 3 years ago
- A Framework for Design and Verification of Image Processing Applications using UVM☆98Updated 7 years ago
- System Verilog based Verification of MIPS 5 staged pipelined processor using UVM environment☆103Updated 4 months ago
- UVM Testbench to verify serial transmission of data between SPI master and slave☆45Updated 4 years ago
- This asynchrounous FIFO deisgn and UVM verificaiton is one case study of me. The design is based on Cliff Cumming's paper and the UVM is…☆60Updated last year
- UART design in SV and verification using UVM and SV☆44Updated 5 years ago
- Presents a verification use case for a typical Asynchronous FIFO based on Systemverilog and UVM.☆50Updated 4 years ago
- UVM AHB VIP☆83Updated 5 months ago
- A Verification Platform for UDP Protocol Ethernet Module wrapped with AXI and APB bus based on UVM☆25Updated 2 years ago
- Attempt to setup a bridge between AHB and I2C by constructing dedicated modules of AHB master , AHB slave , APB master , APB slave, I2C m…☆21Updated 6 years ago
- Built a test environment using SystemVerilog to verify FIFO. Used QuestaSim to design and verify the module in SystemVerilog and Verilog.…☆27Updated 6 years ago
- AXI DMA 32 / 64 bits☆113Updated 10 years ago
- AMBA v.3 APB v.1 Specification Complaint Slave SRAM Core design and testbench. The testbench is developed using System Verilog and UVM an…☆169Updated 6 years ago
- PCIE 5.0 Graduation project (Verification Team)☆71Updated last year
- System Verilog and Emulation. Written all the five channels.☆34Updated 8 years ago
- 支持AXI总线协议的8k×8 SP SRAM☆25Updated 5 years ago
- Verification IP for I2C protocol☆42Updated 3 years ago
- ☆42Updated 3 years ago