raiyyanfaisal09 / AHB_APB-RTLLinks
AHB-APB Bridge RTL Design
☆16Updated 7 years ago
Alternatives and similar repositories for AHB_APB-RTL
Users that are interested in AHB_APB-RTL are comparing it to the libraries listed below
Sorting:
- ☆13Updated 5 years ago
- Maven Silicon project - AHB-to-APB Bridge Verification using UVM Methodology.☆91Updated last year
- The AHB to APB bridge is an AHB slave and the only APB master which provides an interface between the highspeed AHB and the low-power APB…☆61Updated 2 years ago
- Based on ARM AMBA bus protocol, Verilog is used to design the digital circuit.☆127Updated 4 years ago
- VIP for AXI Protocol☆137Updated 3 years ago
- UVM Testbench to verify serial transmission of data between SPI master and slave☆48Updated 4 years ago
- yet another AXI testbench repo. ;) This is for my UVM practice. https://marcoz001.github.io/axi-uvm/☆120Updated 7 years ago
- AXI Interconnect☆50Updated 3 years ago
- Master and Slave made using AMBA AXI4 Lite protocol.☆26Updated 4 years ago
- AMBA AHB 2.0 VIP in SystemVerilog UVM☆151Updated 5 years ago
- UVM examples and projects☆140Updated 6 years ago
- Presents a verification use case for a typical Asynchronous FIFO based on Systemverilog and UVM.☆52Updated 4 years ago
- System Verilog based Verification of MIPS 5 staged pipelined processor using UVM environment☆104Updated 5 months ago
- UVM AHB VIP☆86Updated 7 months ago
- Verification IP for APB protocol☆66Updated 4 years ago
- An uvm verification env for ahb2apb bridge☆53Updated 4 years ago
- AMBA v.3 APB v.1 Specification Complaint Slave SRAM Core design and testbench. The testbench is developed using System Verilog and UVM an…☆172Updated 6 years ago
- Verification IP for I2C protocol☆46Updated 3 years ago
- APB to I2C☆41Updated 10 years ago
- AXI DMA 32 / 64 bits☆113Updated 10 years ago
- A Framework for Design and Verification of Image Processing Applications using UVM☆101Updated 7 years ago
- This repository contains an example of the use of UVM Register Abstraction Layer in a verification of a simple APB DUT.☆41Updated 5 years ago
- ☆36Updated 9 years ago
- ☆43Updated 4 years ago
- This asynchrounous FIFO deisgn and UVM verificaiton is one case study of me. The design is based on Cliff Cumming's paper and the UVM is…☆60Updated last year
- work in SSRL, SOC/NOC/Chiplet Design, DDR/UCIe/PCIe, UVM Framework☆33Updated 2 years ago
- A Verification Platform for UDP Protocol Ethernet Module wrapped with AXI and APB bus based on UVM☆25Updated 3 years ago
- PCIE 5.0 Graduation project (Verification Team)☆76Updated last year
- Attempt to setup a bridge between AHB and I2C by constructing dedicated modules of AHB master , AHB slave , APB master , APB slave, I2C m…☆22Updated 6 years ago
- SystemVerilog-based UVM testbench for an Ethernet 10GE MAC core☆143Updated 6 years ago