freecores / apbi2cLinks
APB to I2C
☆41Updated 10 years ago
Alternatives and similar repositories for apbi2c
Users that are interested in apbi2c are comparing it to the libraries listed below
Sorting:
- Generic AXI to AHB bridge☆17Updated 10 years ago
- AXI Interconnect☆49Updated 3 years ago
- yet another AXI testbench repo. ;) This is for my UVM practice. https://marcoz001.github.io/axi-uvm/☆119Updated 7 years ago
- Maven Silicon project - AHB-to-APB Bridge Verification using UVM Methodology.☆90Updated last year
- ☆36Updated 9 years ago
- UVM AHB VIP☆85Updated 6 months ago
- Verification IP for APB protocol☆66Updated 4 years ago
- A Verification Platform for UDP Protocol Ethernet Module wrapped with AXI and APB bus based on UVM☆25Updated 3 years ago
- Presents a verification use case for a typical Asynchronous FIFO based on Systemverilog and UVM.☆50Updated 4 years ago
- UART design in SV and verification using UVM and SV☆44Updated 5 years ago
- This asynchrounous FIFO deisgn and UVM verificaiton is one case study of me. The design is based on Cliff Cumming's paper and the UVM is…☆60Updated last year
- Attempt to setup a bridge between AHB and I2C by constructing dedicated modules of AHB master , AHB slave , APB master , APB slave, I2C m…☆22Updated 6 years ago
- The AHB to APB bridge is an AHB slave and the only APB master which provides an interface between the highspeed AHB and the low-power APB…☆60Updated 2 years ago
- An uvm verification env for ahb2apb bridge☆53Updated 4 years ago
- PCIE 5.0 Graduation project (Verification Team)☆72Updated last year
- System Verilog based Verification of MIPS 5 staged pipelined processor using UVM environment☆103Updated 5 months ago
- ahb scram controller, design and verification☆27Updated 6 years ago
- AHB DMA 32 / 64 bits☆55Updated 10 years ago
- AXI DMA 32 / 64 bits☆114Updated 10 years ago
- A generic implementation of AMBA AXI4 communication protocol. The design provides a master, a slave and an interconnect with multiple mas…☆38Updated 2 years ago
- This repository contains an example of the use of UVM Register Abstraction Layer in a verification of a simple APB DUT.☆39Updated 4 years ago
- UVM Testbench For SystemVerilog Combinator Implementation☆54Updated 8 years ago
- Based on ARM AMBA bus protocol, Verilog is used to design the digital circuit.☆126Updated 4 years ago
- ☆40Updated last year
- UVM Testbench to verify serial transmission of data between SPI master and slave☆48Updated 4 years ago
- work in SSRL, SOC/NOC/Chiplet Design, DDR/UCIe/PCIe, UVM Framework☆32Updated 2 years ago
- SystemVerilog VIP for AMBA APB protocol☆74Updated 3 years ago
- This is a Multi master Multi slave compatible system bus design modeled using verilog. This is much like AMBA AHB Specification☆32Updated 5 years ago
- AMBA AHB 2.0 VIP in SystemVerilog UVM☆150Updated 5 years ago
- UVM examples and projects☆137Updated 6 years ago