uvm_axi4lite is a uvm package for modeling and verifying AXI4 Lite protocol
☆33Feb 7, 2025Updated last year
Alternatives and similar repositories for uvm_axi4lite
Users that are interested in uvm_axi4lite are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- uvm_starter is a simple template for starting uvm projects☆11Feb 11, 2025Updated last year
- General purpose IO port with AXI4-Lite interface☆10Feb 7, 2025Updated last year
- uvm_axi is a uvm package for modeling and verifying AXI protocol☆21Feb 7, 2025Updated last year
- uvm_apb is a uvm package for modeling and verifying APB (Advanced Periperal Bus) protocol☆21Feb 7, 2025Updated last year
- DDR3 function verification environment in UVM☆26Apr 1, 2018Updated 7 years ago
- Verification IP for APB protocol☆74Dec 18, 2020Updated 5 years ago
- Verification IP for I2C protocol☆51Sep 22, 2021Updated 4 years ago
- RTL implementation of a ray-tracing GPU☆15Dec 18, 2012Updated 13 years ago
- RISC-V vector and tensor compute extensions for Vortex GPGPU acceleration for ML workloads. Optimized for transformer models, CNNs, and g…☆22Apr 25, 2025Updated 10 months ago
- This is for uvm_tb_gen☆52Feb 13, 2025Updated last year
- A small DNN library for RISC-V, using RISC-V Vector and Matrix extensions☆11Mar 13, 2025Updated last year
- ☆12Nov 11, 2015Updated 10 years ago
- Master and Slave made using AMBA AXI4 Lite protocol.☆31Oct 9, 2020Updated 5 years ago
- Generic AHB master stub☆12Jul 17, 2014Updated 11 years ago
- ☆19Aug 11, 2022Updated 3 years ago
- AMBA AXI VIP☆449Jun 28, 2024Updated last year
- A simple UVM example with DPI☆45Aug 7, 2017Updated 8 years ago
- UVM candy lover testbench which uses YASA as simulation script☆17Apr 17, 2020Updated 5 years ago
- Attempt to setup a bridge between AHB and I2C by constructing dedicated modules of AHB master , AHB slave , APB master , APB slave, I2C m…☆22Feb 25, 2019Updated 7 years ago
- Open-source AI Accelerator Stack integrating compute, memory, and software — from RTL to PyTorch.☆25Mar 15, 2026Updated last week
- AXI4 and AXI4-Lite interface definitions☆102Sep 20, 2020Updated 5 years ago
- AES☆15Oct 4, 2022Updated 3 years ago
- Built a test environment using SystemVerilog to verify FIFO. Used QuestaSim to design and verify the module in SystemVerilog and Verilog.…☆36Feb 6, 2019Updated 7 years ago
- uvm AXI BFM(bus functional model)☆267Jun 23, 2013Updated 12 years ago
- yet another AXI testbench repo. ;) This is for my UVM practice. https://marcoz001.github.io/axi-uvm/☆135Nov 29, 2017Updated 8 years ago
- verification of simple axi-based cache☆18May 14, 2019Updated 6 years ago
- Formal Verification of RISC V IM Processor☆10Mar 27, 2022Updated 3 years ago
- fpga based nes box☆22Sep 20, 2021Updated 4 years ago
- AMBA AHB 2.0 VIP in SystemVerilog UVM☆159Mar 31, 2020Updated 5 years ago
- SystemVerilog-based UVM testbench for an Ethernet 10GE MAC core☆160Jul 16, 2018Updated 7 years ago
- my UVM training projects☆39Mar 14, 2019Updated 7 years ago
- ☆43Jan 23, 2026Updated 2 months ago
- System Verilog based Verification of MIPS 5 staged pipelined processor using UVM environment☆119Dec 29, 2024Updated last year
- a very simple risc_cpu verification demo with uvm☆26Apr 28, 2019Updated 6 years ago
- Implemented The UART with FIFO☆15Jul 4, 2019Updated 6 years ago
- A simple implementation about LEGv8 instruction set using Verilog HDL.☆11May 8, 2022Updated 3 years ago
- Maven Silicon Project☆19Oct 13, 2018Updated 7 years ago
- SDRAM controller with AXI4 interface☆103Aug 8, 2019Updated 6 years ago
- Density test bench for RISCV - "Compress extension"☆15Jun 21, 2021Updated 4 years ago