SPI interface connect to APB BUS with Verilog HDL
☆43Jun 27, 2021Updated 5 years ago
Alternatives and similar repositories for verilog_APB_SPI_interface
Users that are interested in verilog_APB_SPI_interface are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- APB to I2C☆45Jul 17, 2014Updated 12 years ago
- Based on ARM AMBA bus protocol, Verilog is used to design the digital circuit.☆150May 14, 2021Updated 5 years ago
- AHB-APB Bridge RTL Design☆16Apr 19, 2018Updated 8 years ago
- ☆58Jun 19, 2021Updated 5 years ago
- AMBA bus lecture material☆558Jan 21, 2020Updated 6 years ago
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting for WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Deploy in minutes on Cloudways by DigitalOcean.
- Interface Protocol in Verilog☆52Aug 2, 2019Updated 7 years ago
- The RTL desings for the AMBA APB3 Master and Generic Slave ( Memory Interface-able )☆19Dec 12, 2025Updated 10 months ago
- A collection of SPI related cores☆23Nov 12, 2024Updated last year
- Implementation of a Serial Peripheral Interface(SPI) using Verilog and testing various modes of the SPI Device☆23Jul 7, 2024Updated 2 years ago
- UVM resource from github, run simulation use YASAsim flow☆33Apr 25, 2020Updated 6 years ago
- 基于FPGA量化的人脸口罩检测☆23Aug 24, 2021Updated 5 years ago
- ARM中通过APB总线连接的UART模块☆72Feb 21, 2020Updated 6 years ago
- ☆14Jun 30, 2019Updated 7 years ago
- Parameterised Asynchronous AHB3-Lite to APB4 Bridge.☆50May 10, 2024Updated 2 years ago
- Virtual machines for every use case on DigitalOcean • AdGet dependable uptime with 99.99% SLA, simple security tools, and predictable monthly pricing with DigitalOcean's virtual machines, called Droplets.
- Synthesizable and Parameterized Cache Controller in Verilog☆49Jun 13, 2023Updated 3 years ago
- A DDR3 Controller that uses the Xilinx MIG-7 PHY to interface with DDR3 devices.☆12Aug 22, 2021Updated 5 years ago
- Chips 2.0 Demo for Atlys Spartan 6 development platform. Web app using C to Verilog TCP/IP server.☆17Jan 10, 2018Updated 8 years ago
- An example OMI Device FPGA with 2 DDR4 memory ports☆20Jan 5, 2023Updated 3 years ago
- Discrete Cosine Transform (DCT) is one of the important image compression algorithms used in image processing applications. Several algor…☆26May 5, 2015Updated 11 years ago
- Generic AHB master stub☆12Jul 17, 2014Updated 12 years ago
- ☆10Aug 12, 2021Updated 5 years ago
- Dual RISC-V DISC with integrated eFPGA☆18Oct 9, 2021Updated 5 years ago
- FFT implementation using CORDIC algorithm written in Verilog.☆36Sep 6, 2018Updated 8 years ago
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting for WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Deploy in minutes on Cloudways by DigitalOcean.
- This is a Multi master Multi slave compatible system bus design modeled using verilog. This is much like AMBA AHB Specification☆32Jan 6, 2020Updated 6 years ago
- 基于w5500官方库ioLibrary_Driver,在STM32F103RC上实现了mqtt的功能☆12Jul 11, 2018Updated 8 years ago
- Verilog Code for I2C Protocol☆20Nov 12, 2020Updated 5 years ago
- RISCV core RV32I/E.4 threads in a ring architecture☆34Jun 12, 2023Updated 3 years ago
- The AHB to APB bridge is an AHB slave and the only APB master which provides an interface between the highspeed AHB and the low-power APB…☆85Oct 7, 2022Updated 4 years ago
- The Repository contains the code of various Digital Circuits☆13Aug 7, 2023Updated 3 years ago
- ☆16Jan 9, 2022Updated 4 years ago
- DDR3 SDRAM Memory Controller Design & Synthesis using System Verilog☆33Nov 6, 2018Updated 7 years ago
- Verification IP for Watchdog☆13Apr 6, 2021Updated 5 years ago
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- TCL, verilog and shell scripts used while learning Cadence genus, innovus and tempus tools.☆17Oct 24, 2021Updated 4 years ago
- - Use FPGA to implement MIPI interface; - Get command from PC through USB communication; - Decode command in FPGA☆13Jul 18, 2017Updated 9 years ago
- ☆14Jun 21, 2026Updated 3 months ago
- A compact, configurable RISC-V core☆13Jul 31, 2025Updated last year
- APB Timer Unit☆14Oct 30, 2025Updated 11 months ago
- [TMI'2022] SASSL☆14May 4, 2023Updated 3 years ago
- RiscSoC 是一个芯片集成项目,包含了 Cortex-M0、Cortex-M3、MIPS、RISC-V、4-BIT 等内核的 SoC 集成,部分 SoC 使用的自己设计的内核☆13Apr 26, 2022Updated 4 years ago