peteut / migen-axi
AXI support for Migen/MiSoC
☆24Updated last month
Related projects: ⓘ
- An experiment for building gateware for the axiom micro / beta using amaranth-hdl☆37Updated 4 months ago
- System on Chip toolkit for nMigen☆19Updated 4 years ago
- Industry standard I/O for nMigen☆12Updated 4 years ago
- Yet Another VHDL tool☆31Updated 7 years ago
- 妖刀夢渡☆55Updated 5 years ago
- FPGA IP cores for the Antikernel OS, intended to be included as a submodule in SoC integrations☆57Updated 3 weeks ago
- ☆57Updated 11 months ago
- Experiments with Yosys cxxrtl backend☆46Updated 8 months ago
- This repository contains iCEBreaker examples for Amaranth HDL.☆36Updated 10 months ago
- lightweight open HLS for FPGA rapid prototyping☆20Updated 6 years ago
- ☆63Updated 4 years ago
- ☆42Updated 5 months ago
- Small footprint and configurable HyperBus core☆10Updated 2 years ago
- Small footprint and configurable SPI core☆38Updated this week
- PicoRV☆43Updated 4 years ago
- My pergola FPGA projects☆30Updated 3 years ago
- 🌉 A transparent Wishbone-to-SPI bridge supporting Execute-In-Place (XIP).☆21Updated 2 years ago
- Next-Generation FPGA Place-and-Route☆10Updated 6 years ago
- ☆13Updated this week
- Tools and Examples for IcoBoard☆79Updated 3 years ago
- Using the TinyFPGA BX USB code in user designs☆49Updated 5 years ago
- OpenFPGA☆33Updated 6 years ago
- Small footprint and configurable Inter-Chip communication cores☆53Updated this week
- chipy hdl☆17Updated 6 years ago
- a noodly Amaranth HDL-wrapper for FPGA SerDes' presenting a PIPE PHY interface☆31Updated 2 years ago
- Using VexRiscv without installing Scala☆34Updated 2 years ago
- A padring generator for ASICs☆22Updated last year
- A demonstration showing how several components can be compsed to build a simulated spectrogram☆39Updated 5 months ago
- Mirror of https://codeberg.org/ECP5-PCIe/ECP5-PCIe