oxidecomputer / quartzLinks
Soft-logic designs and HAL libraries for various subsystems found in Oxide hardware.
☆15Updated last week
Alternatives and similar repositories for quartz
Users that are interested in quartz are comparing it to the libraries listed below
Sorting:
- An FPGA reverse engineering and documentation project☆61Updated this week
- ☆16Updated last year
- Playground for experimenting with and sharing short Amaranth programs on the web☆19Updated last month
- Industry standard I/O for Amaranth HDL☆30Updated last year
- Hot Reconfiguration Technology demo☆41Updated 3 years ago
- Fiber-based SystemVerilog Simulator.☆25Updated 3 years ago
- a noodly Amaranth HDL-wrapper for FPGA SerDes' presenting a PIPE PHY interface☆31Updated 3 years ago
- WebAssembly-based Yosys distribution for Amaranth HDL☆28Updated last week
- A replacement for gtkwave, written in Rust with high-performance and larger-than-memory traces in mind.☆19Updated 3 years ago
- Experiments with Yosys cxxrtl backend☆50Updated 10 months ago
- RFCs for changes to the Amaranth language and standard components☆18Updated last month
- Exploring gate level simulation☆58Updated 7 months ago
- Dual-core RISC-V SoC with JTAG, atomics, SDRAM☆25Updated 3 years ago
- 妖刀夢渡☆63Updated 6 years ago
- Minimal CPU Emulator Powered by the ARM PL080 DMA Controller☆36Updated last year
- System on Chip toolkit for Amaranth HDL☆97Updated last year
- RISC-V out-of-order core for education and research purposes☆81Updated last week
- Small footprint and configurable Inter-Chip communication cores☆66Updated last month
- A collection of little open source FPGA hobby projects☆50Updated 5 years ago
- LiteX LUNA USB stack integration☆14Updated 3 years ago
- Betrusted embedded controller (UP5K)☆48Updated last year
- Open source hardware down to the chip level!☆30Updated 4 years ago
- A Yosys pass and technology library + scripts for implementing a HDL design in discretie FETs for layout in KiCad☆13Updated last year
- Rust proof-of-concept for GPU waveform rendering☆13Updated 5 years ago
- Iron: selectively turn RISC-V binaries into hardware☆23Updated 2 years ago
- Unofficial Yosys WebAssembly packages☆74Updated last week
- RISC-V Processor written in Amaranth HDL☆39Updated 3 years ago
- VexRiscv-SMP integration test with LiteX.☆26Updated 5 years ago
- IP submodules, formatted for easier CI integration☆30Updated 2 months ago
- PicoRV☆43Updated 5 years ago