fjullien / jtag_vpi

Related projects ⓘ

Alternatives and complementary repositories for jtag_vpi

• freecores / jtag
  JTAG Test Access Port (TAP)
  ☆30Updated 10 years ago
• ZipCPU / qspiflash
  A set of Wishbone Controlled SPI Flash Controllers
  ☆76Updated 2 years ago
• aignacio / riscv_verilator_model
  RISCV model for Verilator/FPGA targets
  ☆45Updated 5 years ago
• olofk / wb_intercon
  Wishbone interconnect utilities
  ☆37Updated 5 months ago
• pulp-platform / jtag_dpi
  JTAG DPI module for SystemVerilog RTL simulations
  ☆26Updated 9 years ago
• OVGN / OpenHBMC
  Open-source high performance AXI4-based HyperRAM memory controller
  ☆58Updated 2 years ago
• ultraembedded / core_dbg_bridge
  UART -> AXI Bridge
  ☆57Updated 3 years ago
• dpretet / cdc
  Repository gathering basic modules for CDC purpose
  ☆50Updated 4 years ago
• dmitrodem / p1735_decryptor
  IEEE P1735 decryptor for VHDL
  ☆26Updated 9 years ago
• verilator / verilator-announce
  Announcements related to Verilator
  ☆38Updated 4 years ago
• ultraembedded / core_soc
  Basic Peripheral SoC (SPI, GPIO, Timer, UART)
  ☆58Updated 4 years ago
• RoaLogic / plic
  Platform Level Interrupt Controller
  ☆35Updated 6 months ago
• sergachev / spi_mem_programmer
  Small (Q)SPI flash memory programmer in Verilog
  ☆55Updated 2 years ago
• freecores / ethmac
  Ethernet MAC 10/100 Mbps
  ☆79Updated 5 years ago
• waviousllc / wav-lpddr-hw
  Wavious DDR (WDDR) Physical interface (PHY) Hardware
  ☆98Updated 3 years ago
• chipsalliance / Cores-SweRV_fpga
  ☆39Updated 4 years ago
• www-asics-ws / usb2_dev
  USB 2.0 Device IP Core
  ☆52Updated 7 years ago
• alexforencich / verilog-wishbone
  Verilog wishbone components
  ☆109Updated 10 months ago
• someone755 / ddr3-controller
  A DDR3(L) PHY and controller, written in Verilog, for Xilinx 7-Series FPGAs
  ☆62Updated last year
• RoaLogic / Hamming-ECC
  Hamming ECC Encoder and Decoder to protect memories
  ☆28Updated last month
• fusesoc / fusesoc-cores
  FuseSoC standard core library
  ☆115Updated last month
• rdiez / jtag_dpi
  JTAG DPI module for OpenRISC simulation with Verilator
  ☆16Updated 12 years ago
• BrianHGinc / BrianHG-DDR3-Controller
  DDR3 Controller v1.65, 16 read/write ports, configurable widths, priority, auto-burst size & cache on each port. VGA/HDMI multiwindow vi…
  ☆69Updated 7 months ago
• alexforencich / cocotbext-uart
  UART models for cocotb
  ☆23Updated last year
• buttercutter / DDR
  A simple DDR3 memory controller
  ☆51Updated last year
• open-design / riscv-soc-cores
  ☆37Updated 3 years ago
• olofk / fifo
  Generic FIFO implementation with optional FWFT
  ☆54Updated 4 years ago
• freecores / uart16550
  UART 16550 core
  ☆30Updated 10 years ago
• SpinalHDL / VexRiscvSocSoftware
  ☆26Updated 2 years ago
• ultraembedded / core_usb_host
  Basic USB 1.1 Host Controller for small FPGAs
  ☆85Updated 4 years ago