Alternatives and similar repositories for verilog_fixed_point_math_library

Users that are interested in verilog_fixed_point_math_library are comparing it to the libraries listed below

• alexforencich / verilog-dsp
  Verilog digital signal processing components
  ☆159Updated 3 years ago
• alexforencich / verilog-lfsr
  Fully parametrizable combinatorial parallel LFSR/CRC module
  ☆158Updated 8 months ago
• ahmedshahein / DSP-RTL-Lib
  RTL Verilog library for various DSP modules
  ☆91Updated 3 years ago
• jamieiles / uart
  Verilog UART
  ☆186Updated 12 years ago
• aignacio / ravenoc
  RaveNoC is a configurable HDL NoC (Network-On-Chip) suitable for MPSoCs and different MP applications
  ☆181Updated 11 months ago
• ultraembedded / riscv_soc
  Basic RISC-V Test SoC
  ☆159Updated 6 years ago
• ultraembedded / core_sdram_axi4
  SDRAM controller with AXI4 interface
  ☆98Updated 6 years ago
• ultraembedded / core_soc
  Basic Peripheral SoC (SPI, GPIO, Timer, UART)
  ☆66Updated 5 years ago
• mmxsrup / axi4-interface
  AXI4 and AXI4-Lite interface definitions
  ☆97Updated 5 years ago
• dpretet / async_fifo
  A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog
  ☆388Updated 2 months ago
• raysalemi / Python4RTLVerification
  ☆168Updated 3 years ago
• nanamake / r22sdf
  Pipeline FFT Implementation in Verilog HDL
  ☆142Updated 6 years ago
• freecores / round_robin_arbiter
  round robin arbiter
  ☆76Updated 11 years ago
• taichi-ishitani / tnoc
  Network on Chip Implementation written in SytemVerilog
  ☆193Updated 3 years ago
• nishthaparashar / Floating-Point-ALU-in-Verilog
  32-Bit Algorithms of Floating Point Operations are implemented on Verilog with logic Operations.
  ☆95Updated 6 years ago
• thomasrussellmurphy / stx_cookbook
  Altera Advanced Synthesis Cookbook 11.0
  ☆110Updated 2 years ago
• PulseRain / Reindeer
  PulseRain Reindeer - RISCV RV32I[M] Soft CPU
  ☆127Updated 6 years ago
• OSVVM / AXI4
  AXI4 Full, Lite, and AxiStream verification components. AXI4 Interface Master, Responder, and Memory verification components. AxiStream t…
  ☆143Updated last month
• olofk / fifo
  Generic FIFO implementation with optional FWFT
  ☆60Updated 5 years ago
• alexforencich / cocotbext-axi
  AXI interface modules for Cocotb
  ☆297Updated last month
• dpretet / axi-crossbar
  An AXI4 crossbar implementation in SystemVerilog
  ☆180Updated 2 months ago
• cebarnes / cordic
  An implementation of the CORDIC algorithm in Verilog.
  ☆103Updated 6 years ago
• freecores / dma_axi
  AXI DMA 32 / 64 bits
  ☆122Updated 11 years ago
• adibis / DDR2_Controller
  DDR2 memory controller written in Verilog
  ☆78Updated 13 years ago
• adki / gen_amba
  AMBA bus generator including AXI, AHB, and APB
  ☆106Updated 4 years ago
• taneroksuz / fpu
  IEEE 754 single and double precision floating point library in systemverilog and vhdl
  ☆73Updated 10 months ago
• russdill / bch_verilog
  Verilog based BCH encoder/decoder
  ☆125Updated 3 years ago
• dawsonjon / verilog-math
  Mathematical Functions in Verilog
  ☆95Updated 4 years ago
• RoaLogic / ahb3lite_interconnect
  AHB3-Lite Interconnect
  ☆95Updated last year
• freecores / dma_ahb
  AHB DMA 32 / 64 bits
  ☆56Updated 11 years ago