freecores / verilog_fixed_point_math_libraryLinks
Fixed Point Math Library for Verilog
☆141Updated 11 years ago
Alternatives and similar repositories for verilog_fixed_point_math_library
Users that are interested in verilog_fixed_point_math_library are comparing it to the libraries listed below
Sorting:
- Verilog digital signal processing components☆155Updated 2 years ago
- Fully parametrizable combinatorial parallel LFSR/CRC module☆157Updated 6 months ago
- Altera Advanced Synthesis Cookbook 11.0☆107Updated 2 years ago
- Verilog UART☆180Updated 12 years ago
- RTL Verilog library for various DSP modules☆90Updated 3 years ago
- SDRAM controller with AXI4 interface☆97Updated 6 years ago
- RaveNoC is a configurable HDL NoC (Network-On-Chip) suitable for MPSoCs and different MP applications☆175Updated 9 months ago
- round robin arbiter☆75Updated 11 years ago
- Pipeline FFT Implementation in Verilog HDL☆132Updated 6 years ago
- Basic RISC-V Test SoC☆141Updated 6 years ago
- DDR2 memory controller written in Verilog☆77Updated 13 years ago
- AXI4 and AXI4-Lite interface definitions☆94Updated 4 years ago
- An implementation of the CORDIC algorithm in Verilog.☆99Updated 6 years ago
- A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog☆374Updated last year
- This XUP course provides an introduction to embedded system design on Zynq using the Xilinx Vivado software suite.☆85Updated 2 years ago
- IEEE 754 single and double precision floating point library in systemverilog and vhdl☆69Updated 8 months ago
- 32-Bit Algorithms of Floating Point Operations are implemented on Verilog with logic Operations.☆90Updated 6 years ago
- ☆165Updated 3 years ago
- Network on Chip Implementation written in SytemVerilog☆191Updated 3 years ago
- AXI interface modules for Cocotb☆283Updated last week
- Generic FIFO implementation with optional FWFT☆60Updated 5 years ago
- AXI DMA 32 / 64 bits☆120Updated 11 years ago
- AHB3-Lite Interconnect☆92Updated last year
- An AXI4 crossbar implementation in SystemVerilog☆174Updated 2 weeks ago
- Verilog based BCH encoder/decoder☆123Updated 2 years ago
- AHB DMA 32 / 64 bits☆56Updated 11 years ago
- AMBA bus generator including AXI, AHB, and APB☆106Updated 4 years ago
- Verilog module for calculation of FFT.☆181Updated 13 years ago
- Tool to generate register RTL, models, and docs using SystemRDL or JSpec input☆201Updated 10 months ago
- RISC-V Integration for PYNQ☆174Updated 6 years ago