l-nic / chipyard
An Agile Chisel-Based SoC Design Framework
☆26Updated 3 years ago
Alternatives and similar repositories for chipyard:
Users that are interested in chipyard are comparing it to the libraries listed below
- A Fast, Scalable and Programmable Packet Scheduler in Hardware☆38Updated 5 years ago
- An infrastructure for inline acceleration of network applications☆30Updated 3 years ago
- A Programmable Hardware Architecture for Network Transport Logic☆34Updated 3 years ago
- ☆45Updated 2 years ago
- ☆30Updated 9 years ago
- ☆13Updated last year
- IRN's packet processing logic synthesized using Xilinx Vivado HLS☆22Updated 6 years ago
- Modifications to GEM5 for running kernel bypass networking. (DPDK)☆15Updated last year
- ☆51Updated 7 months ago
- ☆14Updated 7 years ago
- FlowBlaze: Stateful Packet Processing in Hardware☆67Updated 2 years ago
- Flexible, high-performance TCP offload to SmartNICs using fine-grained parallelism☆59Updated 2 years ago
- ☆18Updated last year
- Framework for FPGA-accelerated Middlebox Development☆43Updated 2 years ago
- ESnet SmartNIC hardware design repository.☆45Updated last week
- ☆60Updated last week
- Orignal code/dev history for Menshen paper (NSDI 2022), see https://github.com/multitenancy-project/menshen for official version.☆25Updated 2 years ago
- ☆40Updated 3 months ago
- ☆13Updated 8 months ago
- A machine model for line-rate programmable switches☆24Updated 8 years ago
- P4 compatible HLS modules☆10Updated 6 years ago
- DeepMatch: Practical Deep Packet Inspection in the Data Plane using Network Processors☆15Updated 4 years ago
- ☆32Updated 3 years ago
- ☆57Updated 4 years ago
- PsPIN: A RISC-V in-network accelerator for flexible high-performance low-power packet processing☆101Updated last year
- ☆15Updated last year
- Clio, ASPLOS'22.☆72Updated 3 years ago
- ☆12Updated 2 years ago
- ☆16Updated 3 years ago
- Benchmark Suite for RDMA Performance Isolation☆37Updated last year