spcl / pspinLinks
PsPIN: A RISC-V in-network accelerator for flexible high-performance low-power packet processing
☆103Updated 2 years ago
Alternatives and similar repositories for pspin
Users that are interested in pspin are comparing it to the libraries listed below
Sorting:
- RecoNIC is a software/hardware shell used to enable network-attached processing within an RDMA-featured SmartNIC for scale-out computing.☆139Updated 3 months ago
- AMD OpenNIC driver includes the Linux kernel driver☆67Updated 6 months ago
- ☆64Updated 5 months ago
- FpgaNIC is an FPGA-based Versatile 100Gb SmartNIC for GPUs [ATC 22]☆129Updated last year
- AMD OpenNIC Shell includes the HDL source files☆117Updated 6 months ago
- Alveo Collective Communication Library: MPI-like communication operations for Xilinx Alveo accelerators☆96Updated 2 weeks ago
- Framework for FPGA-accelerated Middlebox Development☆44Updated 2 years ago
- ☆66Updated 2 weeks ago
- The gem5-X open source framework (based on the gem5 simulator)☆41Updated 2 years ago
- Quick & Flexible Rack-Scale Computer Architecture Simulator☆45Updated this week
- A speculative mechanism to accelerate long-latency off-chip load requests by removing on-chip cache access latency from their critical pa…☆71Updated 10 months ago
- Shuhai is a benchmarking-memory tool that allows FPGA programmers to demystify all the underlying details of memories, e.g., HBM and DDR4…☆111Updated last month
- ☆53Updated last year
- Heterogeneous Research Platform (HERO) for exploration of heterogeneous computers consisting of programmable many-core accelerators and a…☆110Updated last year
- ☆92Updated last year
- ☆51Updated 3 years ago
- High Bandwidth Memory (HBM) timing model based on DRAMSim2☆42Updated 7 years ago
- corundum work on vu13p☆19Updated last year
- Framework providing operating system abstractions and a range of shared networking and memory services for common modern heterogeneous pl…☆269Updated last week
- Distributed Accelerator OS☆63Updated 3 years ago
- ☆33Updated 9 years ago
- ☆31Updated last month
- VNx: Vitis Network Examples☆150Updated 11 months ago
- An Agile Chisel-Based SoC Design Framework☆27Updated 3 years ago
- Benchmark suite containing cache filtered traces for use with Ramulator. These include some of the workloads used in our SIGMETRICS 2019 …☆22Updated 4 years ago
- Hands-on experience programming AI Engines using Vitis Unified Software Platform☆41Updated 11 months ago
- An open-source DRAM power model based on extensive experimental characterization of real DRAM modules. Described in the SIGMETRICS 2018 …☆39Updated 6 years ago
- PAAS: A System Level Simulator for Heterogeneous (CPU-FPGA) Computing Systems☆43Updated 3 years ago
- ETHZ Heterogeneous Accelerated Compute Cluster.☆36Updated 3 months ago
- Release of stream-specialization software/hardware stack.☆122Updated 2 years ago