Alternatives and similar repositories for pspin

Users that are interested in pspin are comparing it to the libraries listed below

• RC4ML / FpgaNIC
  FpgaNIC is an FPGA-based Versatile 100Gb SmartNIC for GPUs [ATC 22]
  ☆134Updated 2 years ago
• Xilinx / open-nic-driver
  AMD OpenNIC driver includes the Linux kernel driver
  ☆69Updated 9 months ago
• ETH-PLUS / Jingzhao
  ☆75Updated 2 months ago
• Xilinx / ACCL
  Alveo Collective Communication Library: MPI-like communication operations for Xilinx Alveo accelerators
  ☆97Updated 4 months ago
• pcie-bench / pcie-model
  ☆69Updated 8 months ago
• Xilinx / RecoNIC
  RecoNIC is a software/hardware shell used to enable network-attached processing within an RDMA-featured SmartNIC for scale-out computing.
  ☆148Updated 7 months ago
• esl-epfl / gem5-X
  The gem5-X open source framework (based on the gem5 simulator)
  ☆42Updated 2 years ago
• ucsdsysnet / Rosebud
  Framework for FPGA-accelerated Middlebox Development
  ☆47Updated 2 years ago
• Xilinx / open-nic-shell
  AMD OpenNIC Shell includes the HDL source files
  ☆131Updated 9 months ago
• gthparch / HBM
  High Bandwidth Memory (HBM) timing model based on DRAMSim2
  ☆43Updated 8 years ago
• NetFPGA / NetFPGA-PLUS
  ☆53Updated last year
• OCT-FPGA / OCT-Tutorials
  ☆34Updated last month
• multitenancy-project / menshen
  ☆51Updated 3 years ago
• parsa-epfl / qflex
  Quick & Flexible Rack-Scale Computer Architecture Simulator
  ☆51Updated last week
• minmit / tonic
  A Programmable Hardware Architecture for Network Transport Logic
  ☆35Updated 4 years ago
• l-nic / chipyard
  An Agile Chisel-Based SoC Design Framework
  ☆26Updated 3 years ago
• Krishnaps / Gem5-PCI-Express
  Gem5 with PCI Express integrated.
  ☆21Updated 7 years ago
• programmable-scheduling / pifo-hardware
  ☆35Updated 9 years ago
• Xilinx / xup_vitis_network_example
  VNx: Vitis Network Examples
  ☆154Updated 2 months ago
• SwarmArch / sim
  ordspecsim: The Swarm architecture simulator
  ☆24Updated 2 years ago
• zslwyuan / PAAS_V1.0
  PAAS: A System Level Simulator for Heterogeneous (CPU-FPGA) Computing Systems
  ☆43Updated 4 years ago
• pcie-bench / pciebench-netfpga
  pcie-bench code for NetFPGA/VCU709 cards
  ☆40Updated 7 years ago
• WukLab / Clio
  Clio, ASPLOS'22.
  ☆78Updated 3 years ago
• pgroupATusc / fasthash
  Source Code for the paper Titled FASTHash: FPGA-Based High Throughput Parallel Hash Table published in ISC high performance 2020
  ☆25Updated 3 years ago
• pulp-platform / hero
  Heterogeneous Research Platform (HERO) for exploration of heterogeneous computers consisting of programmable many-core accelerators and a…
  ☆112Updated 2 years ago
• tukl-msd / gem5.TnT
  gem5 Tips & Tricks
  ☆70Updated 5 years ago
• CMU-SAFARI / Hermes
  A speculative mechanism to accelerate long-latency off-chip load requests by removing on-chip cache access latency from their critical pa…
  ☆75Updated last month
• CMU-SAFARI / MemBen
  Benchmark suite containing cache filtered traces for use with Ramulator. These include some of the workloads used in our SIGMETRICS 2019 …
  ☆22Updated 5 years ago
• CMU-SAFARI / VAMPIRE
  An open-source DRAM power model based on extensive experimental characterization of real DRAM modules. Described in the SIGMETRICS 2018 …
  ☆39Updated 6 years ago
• PKUZHOU / NeoMem-MICRO-2024
  The Artifact of NeoMem: Hardware/Software Co-Design for CXL-Native Memory Tiering
  ☆59Updated last year