Alternatives and similar repositories for fpga-kvs

Users that are interested in fpga-kvs are comparing it to the libraries listed below

• POETSII / tinsel
  Manythread RISC-V overlay for FPGA clusters
  ☆38Updated 2 years ago
• fpgasystems / fpga-hyperloglog
  FPGA-based HyperLogLog Accelerator
  ☆12Updated 5 years ago
• fpgasystems / caribou
  Caribou: Distributed Smart Storage built with FPGAs
  ☆67Updated 6 years ago
• fpgasystems / doppiodb
  doppioDB - A hardware accelerated database
  ☆49Updated 8 years ago
• tomahawkins / verilog
  A Verilog parser for Haskell.
  ☆35Updated 4 years ago
• MPACT-ORG / llvm-project
  The LLVM Project is a collection of modular and reusable compiler and toolchain technologies. Note: the repository does not accept github…
  ☆31Updated 3 weeks ago
• camel-cdr / rvv-bench-results
  A collection of RISC-V Vector (RVV) benchmarks to help developers write portably performant RVV code. (Results)
  ☆33Updated last week
• JohnDRO / Golirev-IDE
  An online Verilog IDE based on YosysJS.
  ☆24Updated 9 years ago
• jameshegarty / rigel
  Rigel is a language for describing image processing hardware embedded in Lua. Rigel can compile to Verilog hardware designs for Xilinx FP…
  ☆56Updated 4 years ago
• gokhankici / iodine
  Iodine: Verifying Constant-Time Execution of Hardware
  ☆13Updated 4 years ago
• B-Lang-org / bsc-contrib
  A place to share libraries and utilities that don't belong in the core bsc repo
  ☆35Updated 4 months ago
• Xilinx / nanotube
  ☆105Updated 2 years ago
• zeroasiccorp / umi
  Universal Memory Interface (UMI)
  ☆147Updated last week
• Poofjunior / fpga_fast_serial_sort
  a parallel sorting algorithm implemented in hardware that sorts data in linear time as it arrives serially
  ☆40Updated 9 years ago
• vegaluisjose / reticle-evaluation
  Reticle evaluation (PLDI 2021)
  ☆12Updated 4 years ago
• westerndigitalcorporation / omnixtend
  An open standard Cache Coherent Fabric Interface repository
  ☆66Updated 5 years ago
• rsnikhil / Bluespec_BSV_Formal_Semantics
  Formal semantics of BSV (Bluespec SystemVerilog), given as a Haskell Program and accompanying document
  ☆18Updated 9 years ago
• YosysHQ / VlogHammer
  A Verilog Synthesis Regression Test
  ☆37Updated last year
• f4pga / ideas
  Random ideas and interesting ideas for things we hope to eventually do.
  ☆87Updated 3 years ago
• CTSRD-CHERI / RVBS
  RISC-V BSV Specification
  ☆20Updated 5 years ago
• CTSRD-CHERI / Toooba
  RISC-V Core; superscalar, out-of-order, multi-core capable; based on RISCY-OOO from MIT
  ☆32Updated this week
• johnwickerson / memalloy
  Memory consistency modelling using Alloy
  ☆29Updated 4 years ago
• YosysHQ / abc
  ABC: System for Sequential Logic Synthesis and Formal Verification
  ☆28Updated last week
• YosysHQ / mcy
  Mutation Cover with Yosys (MCY)
  ☆85Updated last week
• cliffordwolf / bextdep
  Reference Hardware Implementations of Bit Extract/Deposit Instructions
  ☆25Updated 7 years ago
• ujamjar / hardcaml-riscv
  RISC-V instruction set CPUs in HardCaml
  ☆15Updated 8 years ago
• lukego / easynic
  EasyNIC: an easy-to-use host interface for network cards
  ☆43Updated 7 years ago
• project-oak / silveroak
  Formal specification and verification of hardware, especially for security and privacy.
  ☆126Updated 3 years ago
• datenlord / wavebpf
  High-performance eBPF implementation in hardware.
  ☆27Updated 3 years ago
• ZipCPU / zipversa
  A Versa Board implementation using the AutoFPGA/ZipCPU infrastructure
  ☆15Updated 5 years ago