Alternatives and similar repositories for fpga-kvs

Users that are interested in fpga-kvs are comparing it to the libraries listed below

• fpgasystems / caribou
  Caribou: Distributed Smart Storage built with FPGAs
  ☆68Updated 7 years ago
• B-Lang-org / bsc-contrib
  A place to share libraries and utilities that don't belong in the core bsc repo
  ☆37Updated 2 months ago
• chipsalliance / omnixtend
  OmniXtend cache coherence protocol
  ☆82Updated 6 months ago
• StanfordVLSI / Genesis2
  A home for Genesis2 sources.
  ☆43Updated 6 months ago
• dovebutch / tlv-comp
  ☆27Updated 10 months ago
• pcie-bench / pciebench-netfpga
  pcie-bench code for NetFPGA/VCU709 cards
  ☆43Updated 7 years ago
• FPGA-Research / byteman
  Bitstream relocation and manipulation tool.
  ☆50Updated 3 years ago
• chipsalliance / fasm
  FPGA Assembly (FASM) Parser and Generator
  ☆99Updated 3 years ago
• antonblanchard / chiselwatt
  A tiny POWER Open ISA soft processor written in Chisel
  ☆112Updated 2 years ago
• antmicro / verilator-uvm-example
  Example of how to use UVM with Verilator
  ☆31Updated last month
• SymbioticEDA / nerv
  Naive Educational RISC-V -- A simple single-stage RV32I processor
  ☆27Updated 5 years ago
• cambridgehackers / connectal
  Connectal is a framework for software-driven hardware development.
  ☆176Updated 2 years ago
• YosysHQ / VlogHammer
  A Verilog Synthesis Regression Test
  ☆37Updated last year
• CESNET / ndk-fpga
  Network Development Kit (NDK) for FPGA cards with example application
  ☆68Updated last week
• ted-xie / REAPR
  REAPR (Reconfigurable Engine for Automata Processing) is a general-purpose framework for accelerating automata processing applications su…
  ☆16Updated 6 years ago
• bluespec / Toooba
  RISC-V Core; superscalar, out-of-order, multi-core capable; based on RISCY-OOO from MIT
  ☆181Updated 8 months ago
• zeroasiccorp / umi
  Universal Memory Interface (UMI)
  ☆156Updated 2 weeks ago
• lewiz-support / LMAC_CORE2
  LeWiz Communications Ethernet MAC Core2 10G/5G/2.5G/1G
  ☆40Updated 2 years ago
• siliconcompiler / zerosoc
  Demo SoC for SiliconCompiler.
  ☆62Updated this week
• YosysHQ / abc
  ABC: System for Sequential Logic Synthesis and Formal Verification
  ☆30Updated last week
• firesim / firechip
  Top-Level Project for Firebox SoC, consisting of Rocket, BOOM, and peripherals (e.g. Ethernet NIC). This is the default target generator …
  ☆56Updated 6 years ago
• drom / reqack
  🔁 elastic circuit toolchain
  ☆32Updated last year
• SymbioticEDA / MARLANN
  Multiply-Accumulate and Rectified-Linear Accelerator for Neural Networks
  ☆91Updated 6 years ago
• KestrelComputer / polaris
  RISC-V RV64IS-compatible processor for the Kestrel-3
  ☆21Updated 2 years ago
• westerndigitalcorporation / swerv_eh1_fpga
  FPGA reference design for the the Swerv EH1 Core
  ☆72Updated 6 years ago
• YosysHQ / yosys-bench
  Benchmarks for Yosys development
  ☆24Updated 5 years ago
• acsl-technion / ntl
  Networking Template Library for Vivado HLS
  ☆29Updated 5 years ago
• pulp-platform / bigpulp
  ⛔ DEPRECATED ⛔ RISC-V manycore accelerator for HERO, bigPULP hardware platform
  ☆50Updated 4 years ago
• schoeberl / lipsi
  Lipsi: Probably the Smallest Processor in the World
  ☆89Updated last year
• azonenberg / antikernel-ipcores
  FPGA IP cores for the Antikernel OS, intended to be included as a submodule in SoC integrations
  ☆69Updated 3 weeks ago