Alternatives and similar repositories for fpga-nvme-controller

Users that are interested in fpga-nvme-controller are comparing it to the libraries listed below

• Xilinx / pcie-model
  PCI Express controller model
  ☆58Updated 2 years ago
• anycore / anycore-riscv-src
  The RTL source for AnyCore RISC-V
  ☆32Updated 3 years ago
• waviousllc / wav-lpddr-sw
  Wavious DDR (WDDR) Physical interface (PHY) Software
  ☆20Updated 3 years ago
• beehive-lab / FastPath_MP
  FastPath_MP: An FPGA-based multi-path architecture for direct access from FPGA to NVMe SSD
  ☆33Updated 4 years ago
• slaclab / axi-pcie-core
  ☆21Updated this week
• adki / cosim_bfm_library
  HW-SW Co-Simulation Library for AMBA AXI BFM using DPI/VPI
  ☆32Updated 6 months ago
• RSPwFPGAs / qemu-hdl-cosim
  VM-HDL Co-Simulation for Servers with PCIe-Connected FPGAs
  ☆48Updated 4 years ago
• b224hisl / rioschip
  ☆33Updated 2 years ago
• oscc-ip / sdram
  An open source SDR SDRAM controller based on the AXI4 bus and verified by FPGA and tapeout. It can support memory particles of different …
  ☆18Updated 2 months ago
• joey1115 / Alpha64_R10000_Superscalar_Processor
  Alpha64 R10000 Two-Way Superscalar Processor
  ☆12Updated 6 years ago
• RISMicroDevices / CHIron
  Open-source AMBA CHI infrastructures (supporting Issue B, E.b)
  ☆19Updated last month
• GabbedT / ApogeoRV
  A RISC-V 32 bits, Out Of Order, single issue with branch prediction CPU, implementing the B, C, M and Zfinx extensions.
  ☆17Updated 3 months ago
• ic-lab-duth / DRIM-S
  DUTH RISC-V Superscalar Microprocessor
  ☆31Updated 8 months ago
• pulp-platform / redundancy_cells
  SystemVerilog IPs and Modules for architectural redundancy designs.
  ☆14Updated this week
• esa-tu-darmstadt / tapasco-riscv
  RISC-V soft-core PEs for TaPaSCo
  ☆22Updated last year
• RSPwFPGAs / virtio-fpga-bridge
  Virtio front-end and back-end bridge, implemented with FPGA.
  ☆28Updated 4 years ago
• giuseppedongiovanni / nvme_comp_storage
  Computational Storage Device based on the open source project OpenSSD.
  ☆26Updated 4 years ago
• pulp-platform / axi_llc
  ☆30Updated last week
• zero-day-labs / riscv-iopmp
  IOPMP IP
  ☆19Updated this week
• mcrl / NVMe
  ☆30Updated last year
• NetTLP / adapter
  An FPGA-based NetTLP adapter
  ☆26Updated 5 years ago
• RoaLogic / Hamming-ECC
  Hamming ECC Encoder and Decoder to protect memories
  ☆33Updated 5 months ago
• pulp-platform / serial_link
  A simple, scalable, source-synchronous, all-digital DDR link
  ☆27Updated 3 weeks ago
• watz0n / arty_xjtag
  Xilinx JTAG Toolchain on Digilent Arty board
  ☆17Updated 7 years ago
• nju-mips / noop-lo
  A simple OoO processor developed by njuallen and wierton, it won 2nd prize in LoongsonCup18.
  ☆28Updated 5 years ago
• ved-rivos / iommu-rtl
  RISC-V IOMMU in verilog
  ☆17Updated 3 years ago
• chipsalliance / caliptra-ss
  HW Design Collateral for Caliptra Subsystem, which comprises Caliptra RoT IP and additional manufacturer controls.
  ☆23Updated this week
• hsa-ees / paranut
  The ParaNut Processor - Highly Parallel and More Than Just a CPU Core
  ☆35Updated 2 years ago
• ultraembedded / core_usb_bridge
  USB -> AXI Debug Bridge
  ☆39Updated 4 years ago
• arpitp / ssd-controller
  Open Source SSD Controller. NVMe and Lightstor variants
  ☆14Updated 11 years ago