Alternatives and similar repositories for fpga-nvme-controller

Users that are interested in fpga-nvme-controller are comparing it to the libraries listed below

• slaclab / axi-pcie-core
  ☆26Updated this week
• Xilinx / pcie-model
  PCI Express controller model
  ☆71Updated 3 years ago
• RSPwFPGAs / qemu-hdl-cosim
  VM-HDL Co-Simulation for Servers with PCIe-Connected FPGAs
  ☆52Updated 5 years ago
• anycore / anycore-riscv-src
  The RTL source for AnyCore RISC-V
  ☆33Updated 3 years ago
• Pufferfish / tlm-of-a-pcie-rootcomplex-systemc
  A transaction level model of a PCI express root complex implemented in systemc
  ☆23Updated 11 years ago
• arpitp / ssd-controller
  Open Source SSD Controller. NVMe and Lightstor variants
  ☆17Updated 11 years ago
• b224hisl / rioschip
  ☆33Updated 3 years ago
• GabbedT / ApogeoRV
  A RISC-V 32 bits, Out Of Order, single issue with branch prediction CPU, implementing the B, C, M and Zfinx extensions.
  ☆20Updated 9 months ago
• adki / cosim_bfm_library
  HW-SW Co-Simulation Library for AMBA AXI BFM using DPI/VPI
  ☆36Updated last year
• mcrl / NVMe
  ☆36Updated 2 years ago
• beehive-lab / FastPath_MP
  FastPath_MP: An FPGA-based multi-path architecture for direct access from FPGA to NVMe SSD
  ☆36Updated 4 years ago
• oscc-ip / sdram
  An open source SDR SDRAM controller based on the AXI4 bus and verified by FPGA and tapeout. It can support memory particles of different …
  ☆21Updated 8 months ago
• AlessandroCilardo / NaplesPU
  The official NaplesPU hardware code repository
  ☆21Updated 6 years ago
• hsa-ees / paranut
  The ParaNut Processor - Highly Parallel and More Than Just a CPU Core
  ☆36Updated 2 years ago
• giuseppedongiovanni / nvme_comp_storage
  Computational Storage Device based on the open source project OpenSSD.
  ☆29Updated 5 years ago
• pulp-platform / axi_llc
  ☆33Updated 2 months ago
• oprecomp / DDR4_controller
  ☆71Updated 4 years ago
• nvdla / tlm2c
  Backup: Library implementing a C TLM-2 style to bridge C models to SystemC TLM-2.0 (C++) from GreenSocs (https://git.greensocs.com/tlm/tl…
  ☆18Updated 7 years ago
• riscveval / Rocket-Chip
  ☆26Updated 8 years ago
• amichai-bd / riscv-multi-core-lotr
  RISCV core RV32I/E.4 threads in a ring architecture
  ☆33Updated 2 years ago
• RSPwFPGAs / virtio-fpga-bridge
  Virtio front-end and back-end bridge, implemented with FPGA.
  ☆28Updated 5 years ago
• pulp-platform / jtag_dpi
  JTAG DPI module for SystemVerilog RTL simulations
  ☆31Updated 10 years ago
• subutai-attic / pars
  ☆30Updated 8 years ago
• himanshu5-prog / vortexGPU
  ☆24Updated 4 years ago
• samehattia / StateMover
  StateMover is a checkpoint-based debugging framework for FPGAs.
  ☆21Updated 3 years ago
• esa-tu-darmstadt / tapasco-riscv
  RISC-V soft-core PEs for TaPaSCo
  ☆23Updated last year
• whutddk / RiftCore
  RiftCore is a 9-stage, single-issue, out-of-order 64-bits RISC-V Core, which supports RV64IMC and 3-level Cache System
  ☆44Updated 3 years ago
• yu-zou / DirectNVM
  An open-source RTL NVMe controller IP for Xilinx FPGA.
  ☆58Updated 4 years ago
• FPGA-Networking / HyperParser
  ☆35Updated 3 years ago
• ic-lab-duth / DRIM-S
  DUTH RISC-V Superscalar Microprocessor
  ☆33Updated last year