goossens-springer / goossens-book-ip-projectsLinks
this repository contains all the ip projects presented in the HLS/RISC-V/Computer Architecture book written by Goossens and published by Springer
☆26Updated last month
Alternatives and similar repositories for goossens-book-ip-projects
Users that are interested in goossens-book-ip-projects are comparing it to the libraries listed below
Sorting:
- Vector processor for RISC-V vector ISA☆128Updated 4 years ago
- ☆98Updated 2 years ago
- RaveNoC is a configurable HDL NoC (Network-On-Chip) suitable for MPSoCs and different MP applications☆179Updated 10 months ago
- Network on Chip Implementation written in SytemVerilog☆191Updated 3 years ago
- Introductory course into static timing analysis (STA).☆97Updated 3 months ago
- Altera Advanced Synthesis Cookbook 11.0☆107Updated 2 years ago
- A Style Guide for the Chisel Hardware Construction Language☆108Updated 4 years ago
- A Fast, Low-Overhead On-chip Network☆228Updated this week
- Two Level Cache Controller implementation in Verilog HDL☆52Updated 5 years ago
- ☆68Updated 2 years ago
- RISC-V Virtual Prototype☆177Updated 9 months ago
- Learn systemC with examples☆121Updated 2 years ago
- An AXI4 crossbar implementation in SystemVerilog☆175Updated last month
- A Chisel RTL generator for network-on-chip interconnects☆211Updated last month
- A dynamic verification library for Chisel.☆155Updated 11 months ago
- RISC-V Verification Interface☆107Updated 2 weeks ago
- RTL Network-on-Chip Router Design in SystemVerilog by Andrea Galimberti, Filippo Testa and Alberto Zeni☆129Updated 7 years ago
- Xilinx AXI VIP example of use☆42Updated 4 years ago
- Advanced Architecture Labs with CVA6☆68Updated last year
- Ariane is a 6-stage RISC-V CPU☆146Updated 5 years ago
- Verilog/SystemVerilog Guide☆73Updated last year
- Verilog Configurable Cache☆184Updated 10 months ago
- Design implementation of the RV32I Core in Verilog HDL with Zicsr extension☆112Updated last year
- Modular Multi-ported SRAM-based Memory☆31Updated 11 months ago
- A demo system for Ibex including debug support and some peripherals☆78Updated 4 months ago
- SystemVerilog modules and classes commonly used for verification☆50Updated 9 months ago
- The objective of this project was to design and implement a 5 stage pipeline CPU to support the RISC-V instruction architecture. This pip…☆26Updated 3 years ago
- Python packages providing a library for Verification Stimulus and Coverage☆127Updated 2 weeks ago
- ☆98Updated last year
- Pequeno (PQR5) is a 5-stage pipelined in-order RISC-V CPU Core compliant with RV32I ISA.☆117Updated last week