RISC-V: Open-source instruction set architecture based on reduced instruction set computer principles.
☆336Mar 12, 2026Updated 2 weeks ago
Alternatives and similar repositories for awesome-riscv-resources
Users that are interested in awesome-riscv-resources are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Curated list of awesome resources related with RISC-V☆96Aug 17, 2022Updated 3 years ago
- Tracking RISC-V Actions on Education, Training, Courses, Monitorships, etc.☆1,487Updated this week
- Complete installation flow of yosys, OpenSTA and OpenROAD for RTL Verification, Synthesis, Timing Analysis, Power Analysis & GDSII layout…☆21Jul 21, 2025Updated 8 months ago
- This repository contains lectures designed for an introduction to RISC-v and it's capabilities.☆10Sep 19, 2025Updated 6 months ago
- ☆13Feb 1, 2025Updated last year
- Virtual machines for every use case on DigitalOcean • AdGet dependable uptime with 99.99% SLA, simple security tools, and predictable monthly pricing with DigitalOcean's virtual machines, called Droplets.
- ☆15Nov 30, 2023Updated 2 years ago
- 32-bit Superscalar RISC-V CPU☆1,207Sep 18, 2021Updated 4 years ago
- The CORE-V CVA6 is a highly configurable, 6-stage RISC-V core for both application and embedded applications. Application class configura…☆2,861Updated this week
- risc-v-myth-workshop-august-Redbeard358 created by GitHub Classroom☆15Sep 15, 2020Updated 5 years ago
- 😎 A curated list of awesome RISC-V implementations☆141Mar 12, 2023Updated 3 years ago
- My 32-bit RISC CPU for smallish FPGAs☆19Apr 20, 2022Updated 3 years ago
- This project is done in the course of "Advanced Physical Design using OpenLANE/Sky130" workshop by VLSI System Design Corporation. In thi…☆56Jul 9, 2021Updated 4 years ago
- Neural Turing Machine for a Multi-Processor System on Chip verified with UVM/OSVVM/FV☆12Mar 22, 2026Updated last week
- ☆21Sep 26, 2025Updated 6 months ago
- Proton VPN Special Offer - Get 70% off • AdSpecial partner offer. Trusted by over 100 million users worldwide. Tested, Approved and Recommended by Experts.
- PicoRV32 - A Size-Optimized RISC-V CPU☆4,044Jun 27, 2024Updated last year
- CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform☆1,203May 26, 2025Updated 10 months ago
- An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more☆2,194Updated this week
- cheriot-ibex is a RTL implementation of CHERIoT ISA based on LowRISC's Ibex core.☆127Mar 6, 2026Updated 3 weeks ago
- CORE-V Family of RISC-V Cores☆341Feb 13, 2025Updated last year
- List of awesome open source hardware tools, generators, and reusable designs☆2,290Mar 2, 2026Updated 3 weeks ago
- FPGA based microcomputer sandbox for software and RTL experimentation☆78Mar 22, 2026Updated last week
- SonicBOOM: The Berkeley Out-of-Order Machine☆2,116Mar 11, 2026Updated 2 weeks ago
- Rocket Chip Generator☆3,730Feb 25, 2026Updated last month
- Virtual machines for every use case on DigitalOcean • AdGet dependable uptime with 99.99% SLA, simple security tools, and predictable monthly pricing with DigitalOcean's virtual machines, called Droplets.
- Verification Template Engine is a Jinja2-based template engine targeted at verification engineers☆14Jan 4, 2024Updated 2 years ago
- Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.☆1,814Feb 17, 2026Updated last month
- A curated list of awesome open source hardware design tools☆86Jun 20, 2025Updated 9 months ago
- KVM RISC-V HowTOs☆47Jun 9, 2022Updated 3 years ago
- ☆12Oct 1, 2021Updated 4 years ago
- Random instruction generator for RISC-V processor verification☆1,270Updated this week
- A minimal Linux-capable 64-bit RISC-V SoC built around CVA6☆324Updated this week
- Berkeley's Spatial Array Generator☆1,261Updated this week
- RISC-V CPU Core☆419Jun 24, 2025Updated 9 months ago
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click and start building anything your business needs.
- The Ultra-Low Power RISC-V Core☆1,787Aug 6, 2025Updated 7 months ago
- The next generation of OpenLane, rewritten from scratch with a modular architecture☆338Dec 2, 2025Updated 3 months ago
- This repository presents the mixed signal design of a Counter Type/ Ramp Type ADC. The Digital part of the circuit i.e 4- bit counter is …☆13May 2, 2022Updated 3 years ago
- ☆17Feb 16, 2023Updated 3 years ago
- Top-Level Project for Firebox SoC, consisting of Rocket, BOOM, and peripherals (e.g. Ethernet NIC). This is the default target generator …☆56Nov 24, 2019Updated 6 years ago
- A FPGA friendly 32 bit RISC-V CPU implementation☆3,090Feb 11, 2026Updated last month
- Functional verification project for the CORE-V family of RISC-V cores.☆666Mar 8, 2026Updated 3 weeks ago