使用Verilog设计的带四舍五入功能的浮点加法器
☆22Dec 19, 2011Updated 14 years ago
Alternatives and similar repositories for Floating-Point-Addition
Users that are interested in Floating-Point-Addition are comparing it to the libraries listed below
Sorting:
- An out-of-order, dual issueed RISC-V core and SOC, a working project.☆10Apr 24, 2023Updated 2 years ago
- ☆14May 15, 2023Updated 2 years ago
- a fast multiplier implement using verilog☆13Dec 23, 2014Updated 11 years ago
- To design test bench of the APB protocol☆18Dec 30, 2020Updated 5 years ago
- Andes Vector Extension support added to riscv-dv☆18May 29, 2020Updated 5 years ago
- double_fpu_verilog☆20Jul 17, 2014Updated 11 years ago
- Verilog Implementation of 32-bit Floating Point Adder☆46May 4, 2020Updated 5 years ago
- This is my hobby project with System Verilog to accelerate LeViT Network which contain CNN and Attention layer.☆33Aug 13, 2024Updated last year
- ☆25Feb 26, 2024Updated 2 years ago
- Network on Chip for MPSoC☆28Jan 27, 2026Updated last month
- ☆24Apr 18, 2021Updated 4 years ago
- ☆27May 11, 2021Updated 4 years ago
- LIS Network-on-Chip Implementation☆34Aug 29, 2016Updated 9 years ago
- PCIe System Verilog Verification Environment developed for PCIe course☆14Mar 26, 2024Updated last year
- Pipelined FFT/IFFT 256 points processor☆10Jul 17, 2014Updated 11 years ago
- AXI3 Bus Functional Models (Initiator & Target)☆30Dec 26, 2022Updated 3 years ago
- Sample UVM code for axi ram dut☆40Dec 14, 2021Updated 4 years ago
- ☆39Dec 8, 2024Updated last year
- 16-bit Adder Multiplier hardware on Digilent Basys 3☆83Aug 3, 2023Updated 2 years ago
- a scaleable ring topology network on chip (NoC) implemented in BSV☆12Oct 14, 2014Updated 11 years ago
- - A 1X3 Router (capable of routing the data packets to three different clients form a single source network) was designed, including a re…☆11Jun 3, 2019Updated 6 years ago
- Language for simplifying parameterized RTL design☆12Nov 6, 2024Updated last year
- verification of the basic router protocol with UVM testbech //INCLUDED WITH RTL☆14Jan 4, 2019Updated 7 years ago
- Ultra High Performance AXI4-based Direct Memory Access (DMA) Controller. This project was an interview assignment. Work in Progress.☆13Oct 19, 2024Updated last year
- Density test bench for RISCV - "Compress extension"☆15Jun 21, 2021Updated 4 years ago
- Single RISC-V CPU attached on AMBA AHB with Instruction and Data memories.☆13Oct 31, 2021Updated 4 years ago
- OpenExSys_NoC a mesh-based network on chip IP.☆20Dec 1, 2023Updated 2 years ago
- Implementation of a Systolic Array based sorting engine on an FPGA using Verilog☆11May 11, 2017Updated 8 years ago
- Design and Verification of a Complete Application Specific Integrated Circuit☆12Nov 21, 2016Updated 9 years ago
- ☆11May 8, 2022Updated 3 years ago
- MAC system with IEEE754 compatibility☆13Nov 22, 2023Updated 2 years ago
- Verilog-Based-NoC-Simulator☆10May 4, 2016Updated 9 years ago
- This is a multi-core processor specially designed for matrix multiplication using Verilog HDL.☆11Jan 8, 2022Updated 4 years ago
- A simple cycle-accurate DaDianNao simulator☆13Mar 27, 2019Updated 6 years ago
- Special Function Units (SFUs) are hardware accelerators, their implementation helps improve the performance of GPUs to process some of th…☆16Sep 21, 2025Updated 5 months ago
- 32-Bit Algorithms of Floating Point Operations are implemented on Verilog with logic Operations.☆99Apr 30, 2019Updated 6 years ago
- A generic implementation of AMBA AXI4 communication protocol. The design provides a master, a slave and an interconnect with multiple mas…☆43Aug 10, 2022Updated 3 years ago
- 位宽和深度可定制的异步FIFO☆14May 29, 2024Updated last year
- RTL code for the DPU chip designed for irregular graphs☆13May 30, 2022Updated 3 years ago