使用Verilog设计的带四舍五入功能的浮点加法器
☆22Dec 19, 2011Updated 14 years ago
Alternatives and similar repositories for Floating-Point-Addition
Users that are interested in Floating-Point-Addition are comparing it to the libraries listed below
Sorting:
- a fast multiplier implement using verilog☆13Dec 23, 2014Updated 11 years ago
- An out-of-order, dual issueed RISC-V core and SOC, a working project.☆10Apr 24, 2023Updated 2 years ago
- Project Trellis database☆14Sep 15, 2025Updated 6 months ago
- ☆14May 15, 2023Updated 2 years ago
- Andes Vector Extension support added to riscv-dv☆18May 29, 2020Updated 5 years ago
- FPGA based motion controller for RepRap style 3D printers☆16May 6, 2013Updated 12 years ago
- This is my hobby project with System Verilog to accelerate LeViT Network which contain CNN and Attention layer.☆34Aug 13, 2024Updated last year
- double_fpu_verilog☆21Jul 17, 2014Updated 11 years ago
- To design test bench of the APB protocol☆18Dec 30, 2020Updated 5 years ago
- AES implementation on FPGA☆13Apr 17, 2016Updated 9 years ago
- ☆25Feb 26, 2024Updated 2 years ago
- 数字图像处理彩色图像复原☆16Jun 21, 2021Updated 4 years ago
- Port of Amber ARM Core project to Marsohod2 platform☆13Dec 4, 2019Updated 6 years ago
- 100道图像处理算法中文版☆13Jul 17, 2020Updated 5 years ago
- Basic floating-point components for RISC-V processors☆12Aug 13, 2017Updated 8 years ago
- Project which creates an analogic sine signal from an architecture that involves FPGA. It were used a DDS core to generate the sine and S…☆15Mar 26, 2014Updated 11 years ago
- ☆24Apr 18, 2021Updated 4 years ago
- Convert single precision float to bfloat16 (Brain Floating Point) floating-point format☆14Oct 24, 2019Updated 6 years ago
- Verilog Gate level Implementation of floating point arithmetic as per IEEE 754☆10May 18, 2021Updated 4 years ago
- RISC-V instruction set CPUs in HardCaml☆15Sep 20, 2016Updated 9 years ago
- A 8-/16-/32-/64-bit floating point number family☆16Feb 4, 2022Updated 4 years ago
- AXI3 Bus Functional Models (Initiator & Target)☆30Dec 26, 2022Updated 3 years ago
- 16-bit Adder Multiplier hardware on Digilent Basys 3☆84Aug 3, 2023Updated 2 years ago
- Language for simplifying parameterized RTL design☆13Nov 6, 2024Updated last year
- A simple app written by Python3 for MMPI☆20Jul 1, 2020Updated 5 years ago
- Design and Verification of a Complete Application Specific Integrated Circuit☆12Nov 21, 2016Updated 9 years ago
- H.264/AVC Baseline Decoder☆16Jul 17, 2014Updated 11 years ago
- Bitstream to Verilog decompiler for Lattice FPGA ECP5 chip.☆23Oct 10, 2021Updated 4 years ago
- Linux programming environment course in Chinese☆12Nov 19, 2017Updated 8 years ago
- ☆28May 11, 2021Updated 4 years ago
- 基于mmpi-2，采用中国常模，附编码型详细解释和剖面图☆15Nov 9, 2025Updated 4 months ago
- 《关于浮点运算：作为程序员都应该了解什么？》☆27Apr 17, 2018Updated 7 years ago
- openMSP430 CPU core (from OpenCores)☆22Oct 14, 2022Updated 3 years ago
- Super scalar Processor design☆21Sep 7, 2014Updated 11 years ago
- Network on Chip for MPSoC☆28Feb 28, 2026Updated 3 weeks ago
- Verilog VGA font generator 8 by 16 pixels☆16Mar 30, 2022Updated 3 years ago
- 支援軒轅劍和仙劍奇俠傳部份作品存檔修改，純瀏覽器上的靜態網頁操作。☆32Updated this week
- The RTL desings for the AMBA APB3 Master and Generic Slave ( Memory Interface-able )☆17Dec 12, 2025Updated 3 months ago
- Recursive unified ORAM☆15Sep 23, 2015Updated 10 years ago