Biinngg / Floating-Point-Addition
使用Verilog设计的带四舍五入功能的浮点加法器
☆20Updated 13 years ago
Alternatives and similar repositories for Floating-Point-Addition:
Users that are interested in Floating-Point-Addition are comparing it to the libraries listed below
- Verilog Code and Logisim simulation of a Weighted Round Robit Arbiter circuit using digital components☆18Updated 6 years ago
- AXI4 and AXI4-Lite interface definitions☆88Updated 4 years ago
- ☆36Updated 6 years ago
- Verilog cache implementation of 4-way FIFO 16k Cache☆19Updated 12 years ago
- round robin arbiter☆70Updated 10 years ago
- AXI DMA 32 / 64 bits☆105Updated 10 years ago
- ☆70Updated 10 years ago
- HDL code for a DDR4 memory controller implementing an Open Page Policy and Out of Order execution.☆73Updated 6 years ago
- AXI总线连接器☆93Updated 4 years ago
- Source code of the paper "Low-Cost and Programmable CRC Implementation based on FPGA"☆42Updated 4 years ago
- ☆27Updated 5 years ago
- FFT generator using Chisel☆57Updated 3 years ago
- AXI3 Bus Functional Models (Initiator & Target)☆27Updated 2 years ago
- AXI4 BFM in Verilog☆31Updated 8 years ago
- 多核处理器 ;ring network , four core, shared space memory ,directory-based cache coherency☆20Updated 8 years ago
- ☆78Updated 2 weeks ago
- AXI master to AHB slave, support INCR/WRAP, out of standing, do not advanced feature such as support out of order, retry, split, etc☆36Updated 2 years ago
- commit rtl and build cosim env☆14Updated 11 months ago
- An AXI4 crossbar implementation in SystemVerilog☆130Updated 2 months ago
- A generic implementation of AMBA AXI4 communication protocol. The design provides a master, a slave and an interconnect with multiple mas…☆31Updated 2 years ago
- ☆63Updated 2 years ago
- ☆38Updated 2 years ago
- ☆16Updated 2 years ago
- Prototype-network-on-chip (ProNoC) is an EDA tool that facilitates prototyping of custom heterogeneous NoC-based many-core-SoC (MCSoC).☆49Updated this week
- work in SSRL, SOC/NOC/Chiplet Design, DDR/UCIe/PCIe, UVM Framework☆28Updated 2 years ago
- a hardware design library based on SpinalHDL, especially for stream processing operators on Xilinx FPGAs for Arithmetic, DSP, Communicati…☆57Updated last year
- A verilog implementation for Network-on-Chip☆71Updated 6 years ago
- System Verilog and Emulation. Written all the five channels.☆32Updated 7 years ago
- Generic AXI to AHB bridge☆16Updated 10 years ago
- AHB DMA 32 / 64 bits☆52Updated 10 years ago