dineshannayya / usb1_hostLinks
USB1.1 Host Controller + PHY
☆14Updated 3 years ago
Alternatives and similar repositories for usb1_host
Users that are interested in usb1_host are comparing it to the libraries listed below
Sorting:
- A 32 bit RISCV Based SOC with QSpi , Uart and 8 bit SDRAM Controller tagetted to efebless shuttle program☆20Updated 2 years ago
- Quad SPI Flash XIP Controller with a direct mapped cache☆11Updated 4 years ago
- SPI-Flash XIP Interface (Verilog)☆38Updated 3 years ago
- WISHBONE DMA/Bridge IP Core☆18Updated 10 years ago
- It is Gate level netlist of MAXVY's MIPI I3C Basic Master Controller IP along with APB interface support.☆17Updated 5 years ago
- ☆21Updated 5 years ago
- Basic Peripheral SoC (SPI, GPIO, Timer, UART)☆63Updated 5 years ago
- DMA core compatible with AHB3-Lite☆10Updated 6 years ago
- A small test SoC for various soft-CPUs (Cortex-M0, RISC-V)☆33Updated 5 years ago
- USB 1.1 Host and Function IP core☆23Updated 10 years ago
- ITMO SystemC & Verilog assignments - AMBA AHB and SPI☆21Updated 7 years ago
- 🐛 JTAG debug transport module (DTM) - compatible to the RISC-V debug specification.☆26Updated 2 years ago
- JTAG DPI module for SystemVerilog RTL simulations☆27Updated 9 years ago
- A VerilogHDL MCU Core based ARMv6 Cortex-M0☆21Updated 5 years ago
- Raptor is an SoC Design Template based on Arm Cortex M0 or M3 core.☆20Updated 5 years ago
- UART -> AXI Bridge☆61Updated 3 years ago
- experimentation with gnu make for Xilinx Vivado compilation. dependencies can be complicated.☆22Updated last year
- Collection of all FPGA related PSI libraries in the correct folder strucutre. Each library is included as submodule.☆34Updated last year
- A port of the DesignStart Cortex-M0 system to the Diligentinc Arty board☆12Updated 6 years ago
- ☆16Updated 6 years ago
- RISC-V compliant Timer IP☆12Updated last year
- I2C controller core☆43Updated 2 years ago
- Extremely basic CortexM0 SoC based on ARM DesignStart Eval☆27Updated 6 years ago
- Wishbone interconnect utilities☆41Updated 3 months ago
- mirror of https://git.elphel.com/Elphel/eddr3☆40Updated 7 years ago
- Multi-Technology RAM with AHB3Lite interface☆23Updated last year
- RISCV model for Verilator/FPGA targets☆53Updated 5 years ago
- An SPI to AXI4-lite bridge for easy interfacing of airhdl register banks with any microcontroller.☆49Updated last year
- Extensible FPGA control platform☆62Updated 2 years ago
- USB Full Speed PHY☆44Updated 5 years ago