dineshannayya / usb1_host
USB1.1 Host Controller + PHY
☆13Updated 3 years ago
Alternatives and similar repositories for usb1_host:
Users that are interested in usb1_host are comparing it to the libraries listed below
- Quad SPI Flash XIP Controller with a direct mapped cache☆11Updated 4 years ago
- A VerilogHDL MCU Core based ARMv6 Cortex-M0☆21Updated 5 years ago
- A 32 bit RISCV Based SOC with QSpi , Uart and 8 bit SDRAM Controller tagetted to efebless shuttle program☆18Updated 2 years ago
- A small test SoC for various soft-CPUs (Cortex-M0, RISC-V)☆31Updated 5 years ago
- Open-source high performance AXI4-based HyperRAM memory controller☆69Updated 2 years ago
- SPI-Flash XIP Interface (Verilog)☆36Updated 3 years ago
- USB Full Speed PHY☆42Updated 4 years ago
- IP Cores that can be used within Vivado☆25Updated 3 years ago
- Wishbone interconnect utilities☆39Updated last month
- A port of the DesignStart Cortex-M0 system to the Diligentinc Arty board☆12Updated 6 years ago
- ☆37Updated 3 years ago
- Basic Peripheral SoC (SPI, GPIO, Timer, UART)☆63Updated 4 years ago
- A set of Wishbone Controlled SPI Flash Controllers☆79Updated 2 years ago
- WISHBONE DMA/Bridge IP Core☆18Updated 10 years ago
- ☆21Updated 5 years ago
- DSP with FPGAs 3. edition ISBN: 978-3-540-72612-8☆14Updated 2 years ago
- It is Gate level netlist of MAXVY's MIPI I3C Basic Master Controller IP along with APB interface support.☆16Updated 5 years ago
- USB 2.0 Device IP Core☆65Updated 7 years ago
- RISCV model for Verilator/FPGA targets☆50Updated 5 years ago
- Raptor is an SoC Design Template based on Arm Cortex M0 or M3 core.☆18Updated 5 years ago
- 🐛 JTAG debug transport module (DTM) - compatible to the RISC-V debug specification.☆26Updated 2 years ago
- JTAG DPI module for SystemVerilog RTL simulations☆27Updated 9 years ago
- An SPI to AXI4-lite bridge for easy interfacing of airhdl register banks with any microcontroller.☆49Updated last year
- ☆25Updated 3 years ago
- DMA core compatible with AHB3-Lite☆10Updated 5 years ago
- Extremely basic CortexM0 SoC based on ARM DesignStart Eval☆25Updated 6 years ago
- 100 MB/s Ethernet MAC Layer Switch☆14Updated 10 years ago
- UART -> AXI Bridge☆60Updated 3 years ago
- IEEE P1735 decryptor for VHDL☆31Updated 9 years ago
- ☆16Updated 5 years ago