YulhwaKim / RRAMScalable_BNNLinks
Neural Network-Hardware Co-design for Scalable RRAM-based BNN Accelerators
☆11Updated 6 years ago
Alternatives and similar repositories for RRAMScalable_BNN
Users that are interested in RRAMScalable_BNN are comparing it to the libraries listed below
Sorting:
- A Unified Framework for Training, Mapping and Simulation of ReRAM-Based Convolutional Neural Network Acceleration☆34Updated 3 years ago
- FracBNN: Accurate and FPGA-Efficient Binary Neural Networks with Fractional Activations☆94Updated 3 years ago
- HLS implemented systolic array structure☆41Updated 7 years ago
- ☆35Updated 5 years ago
- Benchmark framework of compute-in-memory based accelerators for deep neural network (on-chip training chip focused)☆52Updated 4 years ago
- ☆72Updated 2 years ago
- ☆71Updated 5 years ago
- ☆41Updated last year
- RTL implementation of Flex-DPE.☆110Updated 5 years ago
- MAERI: A DNN accelerator with reconfigurable interconnects to support flexible dataflow (http://synergy.ece.gatech.edu/tools/maeri/)☆64Updated 3 years ago
- Neural Network Evaluation Tool on Crossbar-based Accelerator with Resistive Memory☆41Updated 5 years ago
- ☆25Updated last year
- Benchmark framework of compute-in-memory based accelerators for deep neural network (inference engine focused)☆22Updated 4 years ago
- A systolic array simulator for multi-cycle MACs and varying-byte words, with the paper accepted to HPCA 2022.☆80Updated 3 years ago
- ☆28Updated 4 months ago
- An FPGA accelerator for general-purpose Sparse-Matrix Dense-Matrix Multiplication (SpMM).☆83Updated last year
- Simulator for BitFusion☆101Updated 5 years ago
- MICRO22 artifact evaluation for Sparseloop☆44Updated 3 years ago
- Benchmark framework of compute-in-memory based accelerators for deep neural network (inference engine focused)☆72Updated last year
- dMazeRunner: Dataflow acceleration optimization infrastructure for coarse-grained programmable accelerators☆47Updated 3 years ago
- Accelergy is an energy estimation infrastructure for accelerator energy estimations☆147Updated 3 months ago
- A general framework for optimizing DNN dataflow on systolic array☆39Updated 4 years ago
- ☆18Updated 2 years ago
- Benchmark framework of compute-in-memory based accelerators for deep neural network☆43Updated 5 years ago
- A bit-level sparsity-awared multiply-accumulate process element.☆16Updated last year
- ☆34Updated 6 years ago
- Designs for finalist teams of the DAC System Design Contest☆37Updated 5 years ago
- Eyeriss chip simulator☆36Updated 5 years ago
- A Reconfigurable Accelerator with Data Reordering Support for Low-Cost On-Chip Dataflow Switching☆59Updated last week
- PyTorch implementation of DiracDeltaNet from paper Synetgy: Algorithm-hardware Co-design for ConvNet Accelerators on Embedded FPGAs☆32Updated 6 years ago