Alternatives and similar repositories for Digital_Adders_Verilog:

Users that are interested in Digital_Adders_Verilog are comparing it to the libraries listed below

• ac-optimus / Convolution-using-systolic-arrays
  ☆63Updated 6 years ago
• mongrelgem / Verilog-Adders
  Implementing Different Adder Structures in Verilog
  ☆65Updated 5 years ago
• kuladeepsaireddy / OpenNoc
  ☆31Updated 5 years ago
• scale-lab / DRUM
  The Verilog source code for DRUM approximate multiplier.
  ☆30Updated last year
• tharunchitipolu / Dadda-Multiplier-using-CSA
  Dadda multiplier(8*8, 16*16, 32*32) in Verilog HDL.
  ☆34Updated 10 months ago
• suoglu / Fixed-Floating-Point-Adder-Multiplier
  16-bit Adder Multiplier hardware on Digilent Basys 3
  ☆71Updated last year
• kunalg123 / icc2_workshop_collaterals
  This repository has a list of collaterals needed for ICC2 workshop. It has a modified version of raven_soc which was taped-out by Efables…
  ☆31Updated 4 years ago
• aignacio / axi_dma
  General Purpose AXI Direct Memory Access
  ☆49Updated 11 months ago
• bakhshalipour / NoC-Verilog
  A verilog implementation for Network-on-Chip
  ☆73Updated 7 years ago
• hyoukjun / microswitch-noc
  ☆26Updated 5 years ago
• amonemi / ProNoC
  Prototype-network-on-chip (ProNoC) is an EDA tool that facilitates prototyping of custom heterogeneous NoC-based many-core-SoC (MCSoC).
  ☆55Updated last month
• Parimala6 / Floating-point-MAC-verilog
  32 - bit floating point Multiplier Accumulator Unit (MAC)
  ☆30Updated 4 years ago
• ljgibbslf / basic_cache_core
  ☆27Updated 4 years ago
• suhasr1991 / Convolutional-Neural-Network-hardware-using-Verilog
  A project on hardware design for convolutional neural network. This neural network is of 2 layers with 400 inputs in the first layer. Thi…
  ☆18Updated 7 years ago
• StanfordAHA / AhaM3SoC
  SoC Based on ARM Cortex-M3
  ☆30Updated 3 weeks ago
• rgb000000 / eyeriss-chisel3
  eyeriss-chisel3
  ☆40Updated 2 years ago
• pku-dasys / pillars
  An integrated CGRA design framework
  ☆87Updated last month
• neasotho / SystolicArray_FPGA
  Systolic matrix multiplication kernel implemented on Xilinx PYNQ FPGA board
  ☆14Updated 4 years ago
• matutani / nocgen
  NoC (Network-on-Chip) generator that generates Verilog HDL model of NoC consisting of on-chip routers
  ☆62Updated 5 years ago
• Centre-for-Hardware-Security / asap7_reference_design
  reference block design for the ASAP7nm library in Cadence Innovus
  ☆41Updated 10 months ago
• bojackchen / digital-flow
  This is a tutorial on standard digital design flow
  ☆75Updated 3 years ago
• gju06051 / TPU_HW_Verilog
  ☆14Updated 2 years ago
• oprecomp / DDR4_controller
  ☆55Updated 4 years ago
• Liu-Cheng / cycle-accurate-SystemC-simulator-over-ramulator
  An example of using Ramulator as memory model in a cycle-accurate SystemC Design
  ☆49Updated 7 years ago
• abdelrhman-oun / DDR5_PHY_WriteOperation
  ☆50Updated 2 years ago
• pontazaricardo / Verilog_Calculator_Matrix_Multiplication
  This is a simple project that shows how to multiply two 3x3 matrixes in Verilog.
  ☆50Updated 7 years ago
• erihsu / INT_FP_MAC
  INT8 & FP16 multiplier accumulator (MAC) design with UVM verification completed.
  ☆98Updated 4 years ago
• ReuelReuben / vsdSRAM
  SRAM
  ☆22Updated 4 years ago
• louislxw / pe_array
  A linear array of PEs with RISC-V ISA targeting extreme high frequency on Xilinx ZYNQ Ultrascale+, specificially for applications such as…
  ☆10Updated 10 months ago
• VincentWang1998 / ai_on_chip_project1
  tpu-systolic-array-weight-stationary
  ☆24Updated 3 years ago