Ams0x57 / Digital_Adders_VerilogLinks
32 Bit RippleCarry, CarrySkip, CarrySelect, CarryIncrement, Sklansky, Brent-Kung, Kogge-Stone and CarryLookahead adders with their internal components in Verilog
☆25Updated 7 years ago
Alternatives and similar repositories for Digital_Adders_Verilog
Users that are interested in Digital_Adders_Verilog are comparing it to the libraries listed below
Sorting:
- A verilog implementation for Network-on-Chip☆76Updated 7 years ago
- ☆65Updated 6 years ago
- NoC (Network-on-Chip) generator that generates Verilog HDL model of NoC consisting of on-chip routers☆67Updated 5 years ago
- Implementing Different Adder Structures in Verilog☆71Updated 5 years ago
- Project repo for the POSH on-chip network generator☆50Updated 5 months ago
- The Verilog source code for DRUM approximate multiplier.☆31Updated 2 years ago
- ☆34Updated 6 years ago
- General Purpose AXI Direct Memory Access☆58Updated last year
- This is a tutorial on standard digital design flow☆78Updated 4 years ago
- ☆27Updated 5 years ago
- 16-bit Adder Multiplier hardware on Digilent Basys 3☆77Updated 2 years ago
- Dadda multiplier(8*8, 16*16, 32*32) in Verilog HDL.☆34Updated last year
- EE 260 Winter 2017: Advanced VLSI Design☆66Updated 8 years ago
- ☆29Updated 5 years ago
- Prototype-network-on-chip (ProNoC) is an EDA tool that facilitates prototyping of custom heterogeneous NoC-based many-core-SoC (MCSoC).☆59Updated 2 weeks ago
- Source code of the paper "Low-Cost and Programmable CRC Implementation based on FPGA"☆43Updated 4 years ago
- RTL Network-on-Chip Router Design in SystemVerilog by Andrea Galimberti, Filippo Testa and Alberto Zeni☆129Updated 7 years ago
- Design of 1024x32 SRAM (32Kbits) using OpenRAM and SKY130 PDKs with operating voltage of 1.8V and access time < 2.5ns☆75Updated 4 years ago
- SRAM☆22Updated 4 years ago
- SAURIA (Systolic-Array tensor Unit for aRtificial Intelligence Acceleration) is an open-source Convolutional Neural Network accelerator b…☆57Updated 11 months ago
- A project on hardware design for convolutional neural network. This neural network is of 2 layers with 400 inputs in the first layer. Thi…☆18Updated 7 years ago
- IC implementation of TPU☆129Updated 5 years ago
- LCAI-TIHU HW is an AI inference processor which is comprised of RISC-V cpu, nvdla, NoC bus, PCIe module, DDR, SRAM, bootROM, DMA and peri…☆42Updated 2 years ago
- HLS for Networks-on-Chip☆35Updated 4 years ago
- INT8 & FP16 multiplier accumulator (MAC) design with UVM verification completed.☆104Updated 4 years ago
- This is a simple project that shows how to multiply two 3x3 matrixes in Verilog.☆50Updated 8 years ago
- ☆53Updated 6 years ago
- Systolic matrix multiplication kernel implemented on Xilinx PYNQ FPGA board☆14Updated 5 years ago
- The memory model was leveraged from micron.☆22Updated 7 years ago
- sram/rram/mram.. compiler☆39Updated last year