Alternatives and similar repositories for Digital_Adders_Verilog:

Users that are interested in Digital_Adders_Verilog are comparing it to the libraries listed below

• bakhshalipour / NoC-Verilog
  A verilog implementation for Network-on-Chip
  ☆72Updated 7 years ago
• hyoukjun / microswitch-noc
  ☆26Updated 5 years ago
• kuladeepsaireddy / OpenNoc
  ☆31Updated 5 years ago
• suhasr1991 / Convolutional-Neural-Network-hardware-using-Verilog
  A project on hardware design for convolutional neural network. This neural network is of 2 layers with 400 inputs in the first layer. Thi…
  ☆18Updated 7 years ago
• aignacio / axi_dma
  General Purpose AXI Direct Memory Access
  ☆48Updated 10 months ago
• Parimala6 / Floating-point-MAC-verilog
  32 - bit floating point Multiplier Accumulator Unit (MAC)
  ☆29Updated 4 years ago
• amonemi / ProNoC
  Prototype-network-on-chip (ProNoC) is an EDA tool that facilitates prototyping of custom heterogeneous NoC-based many-core-SoC (MCSoC).
  ☆53Updated 2 weeks ago
• scale-lab / DRUM
  The Verilog source code for DRUM approximate multiplier.
  ☆29Updated last year
• mongrelgem / Verilog-Adders
  Implementing Different Adder Structures in Verilog
  ☆64Updated 5 years ago
• erihsu / INT_FP_MAC
  INT8 & FP16 multiplier accumulator (MAC) design with UVM verification completed.
  ☆94Updated 4 years ago
• ac-optimus / Convolution-using-systolic-arrays
  ☆63Updated 6 years ago
• suoglu / Fixed-Floating-Point-Adder-Multiplier
  16-bit Adder Multiplier hardware on Digilent Basys 3
  ☆70Updated last year
• kunalg123 / icc2_workshop_collaterals
  This repository has a list of collaterals needed for ICC2 workshop. It has a modified version of raven_soc which was taped-out by Efables…
  ☆30Updated 4 years ago
• ehw-fit / ariths-gen
  Generator of arithmetic circuits (multipliers, adders) and approximate circuits
  ☆31Updated 2 months ago
• tej-chavan / Design-and-Verification-of-DDR3-Memory-Controller
  The memory model was leveraged from micron.
  ☆22Updated 7 years ago
• VincentWang1998 / ai_on_chip_project1
  tpu-systolic-array-weight-stationary
  ☆23Updated 3 years ago
• anan-cn / Open-Source-Network-on-Chip-Router-RTL
  ☆72Updated 10 years ago
• leo47007 / TPU-Tensor-Processing-Unit
  IC implementation of TPU
  ☆114Updated 5 years ago
• StanfordAHA / AhaM3SoC
  SoC Based on ARM Cortex-M3
  ☆29Updated 3 weeks ago
• ryaanluke / DNN-Hardware-Accelerator
  SystemVerilog files for lab project on a DNN hardware accelerator
  ☆16Updated 3 years ago
• louislxw / pe_array
  A linear array of PEs with RISC-V ISA targeting extreme high frequency on Xilinx ZYNQ Ultrascale+, specificially for applications such as…
  ☆10Updated 9 months ago
• MorrisMA / Booth_Multipliers
  Parameterized Booth Multiplier in Verilog 2001
  ☆49Updated 2 years ago
• rgb000000 / eyeriss-chisel3
  eyeriss-chisel3
  ☆40Updated 2 years ago
• maomran / softmax
  Verilog implementation of Softmax function
  ☆62Updated 2 years ago
• pontazaricardo / Verilog_Calculator_Matrix_Multiplication
  This is a simple project that shows how to multiply two 3x3 matrixes in Verilog.
  ☆50Updated 7 years ago
• abdelrhman-oun / DDR5_PHY_WriteOperation
  ☆45Updated 2 years ago
• Centre-for-Hardware-Security / asap7_reference_design
  reference block design for the ASAP7nm library in Cadence Innovus
  ☆41Updated 9 months ago
• VenciFreeman / FFT_ChipDesign
  A 16-point radix-4 FFT chip, including Verilog codes, netlists and layout. Group project.
  ☆60Updated 7 months ago
• ljgibbslf / basic_cache_core
  ☆26Updated 4 years ago
• romulus0914 / CNN_VGG19_verilog
  Convolution Neural Network of vgg19 model in verilog
  ☆46Updated 7 years ago