Ams0x57 / Digital_Adders_Verilog
32 Bit RippleCarry, CarrySkip, CarrySelect, CarryIncrement, Sklansky, Brent-Kung, Kogge-Stone and CarryLookahead adders with their internal components in Verilog
☆24Updated 7 years ago
Alternatives and similar repositories for Digital_Adders_Verilog
Users that are interested in Digital_Adders_Verilog are comparing it to the libraries listed below
Sorting:
- A verilog implementation for Network-on-Chip☆73Updated 7 years ago
- ☆33Updated 6 years ago
- ☆64Updated 6 years ago
- HLS for Networks-on-Chip☆34Updated 4 years ago
- ☆27Updated 5 years ago
- General Purpose AXI Direct Memory Access☆49Updated last year
- SoC Based on ARM Cortex-M3☆30Updated last week
- The Verilog source code for DRUM approximate multiplier.☆30Updated 2 years ago
- 16-bit Adder Multiplier hardware on Digilent Basys 3☆74Updated last year
- Prototype-network-on-chip (ProNoC) is an EDA tool that facilitates prototyping of custom heterogeneous NoC-based many-core-SoC (MCSoC).☆56Updated 2 months ago
- Implementing Different Adder Structures in Verilog☆67Updated 5 years ago
- A linear array of PEs with RISC-V ISA targeting extreme high frequency on Xilinx ZYNQ Ultrascale+, specificially for applications such as…☆10Updated 11 months ago
- This repository has a list of collaterals needed for ICC2 workshop. It has a modified version of raven_soc which was taped-out by Efables…☆31Updated 4 years ago
- SAURIA (Systolic-Array tensor Unit for aRtificial Intelligence Acceleration) is an open-source Convolutional Neural Network accelerator b…☆41Updated 7 months ago
- Source code of the paper "Low-Cost and Programmable CRC Implementation based on FPGA"☆42Updated 4 years ago
- ☆65Updated 3 years ago
- LCAI-TIHU HW is an AI inference processor which is comprised of RISC-V cpu, nvdla, NoC bus, PCIe module, DDR, SRAM, bootROM, DMA and peri…☆37Updated 2 years ago
- INT8 & FP16 multiplier accumulator (MAC) design with UVM verification completed.☆100Updated 4 years ago
- FFT generator using Chisel☆59Updated 3 years ago
- 32 - bit floating point Multiplier Accumulator Unit (MAC)☆30Updated 4 years ago
- The memory model was leveraged from micron.☆22Updated 7 years ago
- tpu-systolic-array-weight-stationary☆24Updated 4 years ago
- NoC (Network-on-Chip) generator that generates Verilog HDL model of NoC consisting of on-chip routers☆62Updated 5 years ago
- Dadda multiplier(8*8, 16*16, 32*32) in Verilog HDL.☆34Updated 11 months ago
- A Verilog design of LeNet-5, a Convolutional Neural Network architecture☆32Updated 4 years ago
- Bitonic sorter (Batcher's sorting network) written in Verilog.☆32Updated 7 months ago
- Verilog Implementation of 32-bit Floating Point Adder☆40Updated 5 years ago
- AXI master to AHB slave, support INCR/WRAP, out of standing, do not advanced feature such as support out of order, retry, split, etc☆41Updated 3 years ago
- eyeriss-chisel3☆40Updated 3 years ago
- This is a simple project that shows how to multiply two 3x3 matrixes in Verilog.☆49Updated 7 years ago