Using ModelSim Foreign Language Interface for c – VHDL Co-Simulation and for Simulator Control on Linux x86 Platform
☆28Dec 17, 2020Updated 5 years ago
Alternatives and similar repositories for fli
Users that are interested in fli are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- ☆15Sep 14, 2020Updated 5 years ago
- Example Projects for the Microsemi SmartFusion 2☆11Dec 10, 2017Updated 8 years ago
- This is an example of how TerosHDL can generate your documentation project from the command line. So you can integrate it in your CI work…☆10Jan 13, 2022Updated 4 years ago
- GitHub-based statistics highlighting interesting facts about the HDL industry☆12Jul 6, 2023Updated 3 years ago
- Utilities for Avalon Memory Map☆11Jun 16, 2026Updated last month
- AI Agents on DigitalOcean Gradient AI Platform • AdBuild production-ready AI agents using customizable tools or access multiple LLMs through a single endpoint. Create custom knowledge bases or connect external data.
- GHDL Verilator Interface. A glue code generator for VHDL Verilog cosimulation.☆17Apr 10, 2025Updated last year
- Generic AXI interconnect fabric☆13Jul 17, 2014Updated 12 years ago
- Flexible VHDL library☆198Jun 28, 2023Updated 3 years ago
- ☆17Sep 14, 2023Updated 2 years ago
- An IP-XACT DOM for IEEE 1685-2014 in Python.☆31Jul 21, 2026Updated 3 weeks ago
- VHDL dependency analyzer☆25Mar 10, 2020Updated 6 years ago
- 控制组生存指南☆10Jun 28, 2019Updated 7 years ago
- Sphinx extension for visual documentation of hardware written in HWT☆12Nov 12, 2025Updated 9 months ago
- Common code library☆15Feb 3, 2018Updated 8 years ago
- GPU virtual machines on DigitalOcean Gradient AI • AdGet to production fast with high-performance AMD and NVIDIA GPUs you can spin up in seconds. The definition of operational simplicity.
- nextpnr portable FPGA place and route tool☆11Nov 30, 2020Updated 5 years ago
- =nil; Foundation's Algebraic Operations and Structures Module☆10May 26, 2024Updated 2 years ago
- Doxygen with verilog support☆41Mar 15, 2019Updated 7 years ago
- vhdl related contents☆11Apr 27, 2020Updated 6 years ago
- Cloneless1 is an open-source tamper-resistant cryptographic ASIC design☆24Jul 30, 2026Updated 2 weeks ago
- Portable HyperRAM controller☆69Dec 8, 2024Updated last year
- 一个最基础的使用tauri和react开发跨平台应用软件的架子，支持自定义头部和窗口阴影，非常的nice好用☆12Sep 3, 2023Updated 2 years ago
- A high-throughput VHDL and SystemVerilog implementation of AES-128 including scripts for a full front-end design process.☆43Nov 17, 2014Updated 11 years ago
- Style guide enforcement for VHDL☆249Jul 24, 2026Updated 3 weeks ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- Streaming based VHDL parser.☆86Jul 15, 2024Updated 2 years ago
- Openhardware educational platform based on the ideas of the ulx3s and Gecko4Education☆16Jul 16, 2025Updated last year
- Virtual development board for HDL design☆42Mar 31, 2023Updated 3 years ago
- Dockerfile with Vivado for CI☆63Jun 26, 2017Updated 9 years ago
- Kasli is a powerful FPGA carrier, capable of controlling 12 Eurocard extension modules.☆21Sep 15, 2025Updated 10 months ago
- A customized copy of OpenOCD able to access the jtagd/jtagserver distributed with Quartus. At present it is restricted to accessing the A…☆12Aug 18, 2025Updated 11 months ago
- A DMA Controller for RISCV CPUs☆13Aug 10, 2015Updated 11 years ago
- ☆33Jul 15, 2026Updated 3 weeks ago
- Small example demonstrating overlay windows with accessibility service on Android.☆11Apr 22, 2021Updated 5 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- ☆17Jul 12, 2020Updated 6 years ago
- Examples of unions, interfaces, and assertions in SystemVerilog☆13Aug 31, 2013Updated 12 years ago
- PolarFire FPGA sample RISC-V designs☆14Oct 15, 2019Updated 6 years ago
- A project created for XiDianUniversity☆13Sep 3, 2016Updated 9 years ago
- Repository of FPGA from Zero to Hero - Live and Free FPGA/SoC Lectures on YouTube (www.youtube.com/@falsepaths)☆36Jul 24, 2025Updated last year
- Website!☆11Aug 29, 2020Updated 5 years ago
- An open source applicaton for CAN bus analysis, testing and data acquisition☆11Feb 12, 2017Updated 9 years ago