Kkalais / Hardware-Trojan-DetectionLinks
Machine Learning Techniques for Hardware Trojan Detection
☆27Updated 5 years ago
Alternatives and similar repositories for Hardware-Trojan-Detection
Users that are interested in Hardware-Trojan-Detection are comparing it to the libraries listed below
Sorting:
- ☆47Updated 2 years ago
- ☆17Updated 2 years ago
- CocoAlma is an execution-aware tool for formal verification of masked implementations☆23Updated last year
- RISCV MYTH 4 stage pipelined core designed using TL-Verilog and supports RV32I base integer instruction set☆15Updated 5 years ago
- ☆14Updated 5 years ago
- AutoSVA is a tool to automatically generate formal testbenches for unit-level RTL verification. The goal is to, based on annotations made…☆98Updated last year
- Methodology that leverages FPV to automatically discover covert channels in hardware that is time-shared between processes. AutoCC operat…☆22Updated last year
- ANSI-C benchmarks generated from Verilog RTL circuits with safety assertions. Used for Formal Property Verification.☆17Updated 7 years ago
- Benchmarks for Approximate Circuit Synthesis☆17Updated 5 years ago
- ☆14Updated 3 years ago
- SIMPLE MAGIC: Synthesis and In-memory MaPping of Logic Execution for Memristor Aided loGIC☆15Updated 5 years ago
- ☆16Updated 2 years ago
- GNN-RE datasets for circuit recognition☆56Updated 2 years ago
- ASIC Design kit for Skywater 130 for use with mflowgen☆14Updated 2 years ago
- ☆10Updated 4 years ago
- A Formal Verification Framework for Chisel☆18Updated last year
- Used for hardware trojan detection（Based on Trust_Hub）☆10Updated 6 years ago
- A fork of Yosys that integrates the CellIFT pass☆13Updated 5 months ago
- C++ and Verilog to implement AES128☆24Updated 7 years ago
- Wallace and Dadda tree multiplier generator in vhdl and verilog☆11Updated last year
- SMT Attack☆22Updated 4 years ago
- A RISC-V RV32 model ready for SMT program synthesis.☆12Updated 4 years ago
- ☆20Updated last year
- ☆13Updated 4 years ago
- Digital Standard Cells based SAR ADC☆14Updated 4 years ago
- Hardware Formal Verification☆17Updated 5 years ago
- Awesome machine learning for logic synthesis☆30Updated 3 years ago
- VeRLPy is an open-source python library developed to improve the digital hardware verification process by using Reinforcement Learning (R…☆30Updated 3 years ago
- Generator of arithmetic circuits (multipliers, adders) and approximate circuits☆39Updated 5 months ago
- A Modular Open-Source Hardware Fuzzing Framework☆36Updated 4 years ago