Alternatives and similar repositories for Hardware-Trojan-Detection:

Users that are interested in Hardware-Trojan-Detection are comparing it to the libraries listed below

• AICPS / hw2vec
  ☆37Updated last year
• Crimsonninja / senior_design_puf
  Repository to store all design and testbench files for Senior Design
  ☆17Updated 4 years ago
• ekiwi / open-source-formal-verification-for-chisel
  ☆12Updated 3 years ago
• DfX-NYUAD / GNN-RE
  GNN-RE datasets for circuit recognition
  ☆40Updated last year
• IAIK / coco-alma
  CocoAlma is an execution-aware tool for formal verification of masked implementations
  ☆21Updated 4 months ago
• momalab / CoPHEE
  CoPHEE is a Co-processor for Partially Homomorphic Encrypted Encryption.
  ☆28Updated 11 months ago
• scale-lab / BACS
  Benchmarks for Approximate Circuit Synthesis
  ☆15Updated 4 years ago
• nolancon / AES128
  C++ and Verilog to implement AES128
  ☆19Updated 6 years ago
• nputikhin / sat_atpg
  SAT-based ATPG using TG-Pro model
  ☆15Updated 6 years ago
• RotemBenHur / SIMPLE-MAGIC
  SIMPLE MAGIC: Synthesis and In-memory MaPping of Logic Execution for Memristor Aided loGIC
  ☆14Updated 5 years ago
• PrincetonUniversity / AutoSVA
  AutoSVA is a tool to automatically generate formal testbenches for unit-level RTL verification. The goal is to, based on annotations made…
  ☆75Updated 10 months ago
• sterin / super-prove-build
  ☆11Updated 4 years ago
• khushhallchandra / Simulated-Annealing
  Simulated Annealing to minimize the wirelength
  ☆8Updated 7 years ago
• gpt4rtl / AutoSVA2
  ☆12Updated last year
• tharunchitipolu / Dadda-Multiplier-using-CSA
  Dadda multiplier(8*8, 16*16, 32*32) in Verilog HDL.
  ☆34Updated 7 months ago
• cure-lab / DeepGate2
  ☆14Updated last year
• vinayrayapati / iiitb_rv32i
  ☆13Updated 2 years ago
• siamumar / BIST_PUF_TRNG
  A Built-in-Self-Test Scheme for Online Evaluation of Physical Unclonable Functions and True Random Number Generators
  ☆21Updated 7 years ago
• ehw-fit / ariths-gen
  Generator of arithmetic circuits (multipliers, adders) and approximate circuits
  ☆30Updated last week
• jpsety / verilog_benchmark_circuits
  EPFL and ISCAS85 combinational benchmark circuits in generic gate verilog
  ☆24Updated 5 years ago
• AnuragSChatterjee / Multilayer-Perception-MLP-Neural-Network-Implementation-In-FPGA
  A final semester based group project for EE4218: Embedded Hardware System Design module in NUS where I worked with my teammate to perform…
  ☆12Updated last year
• aebeljs / VeRLPy
  VeRLPy is an open-source python library developed to improve the digital hardware verification process by using Reinforcement Learning (R…
  ☆25Updated 2 years ago
• amamory-verification / hw-formal-verif
  Hardware Formal Verification
  ☆15Updated 4 years ago
• Moorvan / ChiselFV
  A Formal Verification Framework for Chisel
  ☆18Updated 9 months ago
• DfX-NYUAD / GNN4IC
  Must-read papers on Graph Neural Networks (GNNs) for Integrated Circuits (ICs) design, security and reliability. This collection of paper…
  ☆43Updated last year
• lnestor / sat_attack
  A basic implementation of a SAT attack on logic locking.
  ☆12Updated 3 years ago
• efeslab / hardware-bugbase
  ☆17Updated 7 months ago
• wvangansbeke / High-Level-Synthesis
  Convert C files into Verilog
  ☆16Updated 6 years ago
• black-parrot-hdk / zynq-parrot
  BlackParrot on Zynq
  ☆25Updated last week
• openformal / sva_basics
  This repository is compilation of basics of System Verilog Assertions in context of formal verification
  ☆20Updated 5 years ago