Alternatives and similar repositories for Hardware-Trojan-Detection

Users that are interested in Hardware-Trojan-Detection are comparing it to the libraries listed below

• AICPS / hw2vec
  ☆42Updated 2 years ago
• gpt4rtl / AutoSVA2
  ☆17Updated last year
• ekiwi / open-source-formal-verification-for-chisel
  ☆10Updated 3 years ago
• rajdeep87 / verilog-c
  ANSI-C benchmarks generated from Verilog RTL circuits with safety assertions. Used for Formal Property Verification.
  ☆15Updated 6 years ago
• isec-tugraz / coco-alma
  CocoAlma is an execution-aware tool for formal verification of masked implementations
  ☆22Updated 11 months ago
• skmuduli92 / HyperFuzzer
  ☆16Updated 4 years ago
• efeslab / hardware-bugbase
  ☆18Updated last year
• sterin / super-prove-build
  ☆13Updated 4 years ago
• morenes / AutoCC
  Methodology that leverages FPV to automatically discover covert channels in hardware that is time-shared between processes. AutoCC operat…
  ☆20Updated 10 months ago
• ShonTaware / RISC-V_Core_4_Stage
  RISCV MYTH 4 stage pipelined core designed using TL-Verilog and supports RV32I base integer instruction set
  ☆15Updated 4 years ago
• PrincetonUniversity / AutoSVA
  AutoSVA is a tool to automatically generate formal testbenches for unit-level RTL verification. The goal is to, based on annotations made…
  ☆88Updated last year
• Moorvan / ChiselFV
  A Formal Verification Framework for Chisel
  ☆18Updated last year
• hkust-zhiyao / NetTAG
  NetTAG: A Multimodal RTL-and-Layout-Aligned Netlist Foundation Model via Text-Attributed Graph (DAC'25)
  ☆14Updated 2 weeks ago
• Moorvan / RISCV-Formal-Chisel
  RISC-V Formal in Chisel
  ☆11Updated last year
• hammad-a / verilog_repair
  Automated Repair of Verilog Hardware Descriptions
  ☆33Updated 7 months ago
• Entropy-xcy / sns
  ☆19Updated 2 years ago
• cure-lab / DeepGate2
  ☆15Updated 2 years ago
• iscas-tis / CHA
  ☆19Updated last year
• facebookresearch / AutoCAT
  AutoCAT: Reinforcement Learning for Automated Exploration of Cache-Timing Attacks
  ☆46Updated 2 years ago
• achieve-lab / assertion_data_for_LLM
  ☆16Updated 7 months ago
• hkust-zhiyao / AssertLLM
  Generating Hardware Verification Assertions from Design Specifications via Multi-LLMs
  ☆38Updated 10 months ago
• NVlabs / FVEval
  LLM Evaluation Benchmark on Hardware Formal Verification
  ☆29Updated 5 months ago
• ics-jku / epex-formal-rv32-model
  A RISC-V RV32 model ready for SMT program synthesis.
  ☆12Updated 4 years ago
• rzhang2285 / Coppelia
  Code repository for Coppelia tool
  ☆23Updated 4 years ago
• gatelabdavis / SMTAttack
  SMT Attack
  ☆21Updated 4 years ago
• aebeljs / VeRLPy
  VeRLPy is an open-source python library developed to improve the digital hardware verification process by using Reinforcement Learning (R…
  ☆27Updated 2 years ago
• amamory-verification / hw-formal-verif
  Hardware Formal Verification
  ☆15Updated 5 years ago
• scale-lab / BACS
  Benchmarks for Approximate Circuit Synthesis
  ☆17Updated 5 years ago
• OSCC-Project / iMap
  Logic optimization and technology mapping tool.
  ☆19Updated last year
• Chenghao-Yang / awesome-ml4ls
  Awesome machine learning for logic synthesis
  ☆29Updated 2 years ago