Machine Learning Techniques for Hardware Trojan Detection
☆28Sep 24, 2020Updated 6 years ago
Alternatives and similar repositories for Hardware-Trojan-Detection
Users that are interested in Hardware-Trojan-Detection are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Used for hardware trojan detection（Based on Trust_Hub）☆10Jul 30, 2019Updated 7 years ago
- TrojanSAINT: Gate-Level Netlist Sampling-Based Inductive Learning for Hardware Trojan Detection☆23Oct 3, 2023Updated 2 years ago
- ☆55Jul 6, 2023Updated 3 years ago
- ☆16Sep 14, 2020Updated 6 years ago
- Graph your gate-level verilog code as a directed graph!☆17Nov 3, 2020Updated 5 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- ANSI-C benchmarks generated from Verilog RTL circuits with safety assertions. Used for Formal Property Verification.☆17Dec 1, 2018Updated 7 years ago
- GNN-RE datasets for circuit recognition☆61May 16, 2023Updated 3 years ago
- Random Generator of Btor2 Files☆10Sep 2, 2023Updated 3 years ago
- RISCV MYTH 4 stage pipelined core designed using TL-Verilog and supports RV32I base integer instruction set☆16Jan 14, 2021Updated 5 years ago
- A basic implementation of a SAT attack on logic locking.☆13Jun 30, 2021Updated 5 years ago
- ☆10Oct 15, 2021Updated 4 years ago
- RISC-V Formal in Chisel☆13Apr 9, 2024Updated 2 years ago
- This is a probabilistic SAT attack tool.☆13Jun 5, 2021Updated 5 years ago
- Python version of tools to work with AIG formatted files☆13Sep 7, 2026Updated 2 weeks ago
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting for WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Deploy in minutes on Cloudways by DigitalOcean.
- AXI Formal Verification IP☆25Apr 28, 2021Updated 5 years ago
- Research project from UCI's AICPS lab: using GNNs to enable hardware security and prevent hardware trojans☆10Mar 31, 2021Updated 5 years ago
- ☆15Feb 6, 2021Updated 5 years ago
- Bᴛᴏʀ2MLIR: A Format and Toolchain for Hardware Verification☆20Jul 8, 2026Updated 2 months ago
- QuteRTL: A RTL Front-End Towards Intelligent Synthesis and Verification☆18Nov 8, 2016Updated 9 years ago
- A generic parser and tool package for the BTOR2 format.☆50Updated this week
- ☆18Nov 9, 2022Updated 3 years ago
- ☆21Updated this week
- Optimal gate sizing of digital circuits using geometric programming☆11Aug 18, 2016Updated 10 years ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- A chess implementation in C++ with many player AIs, including a neural-network-powered AI not unlike Deepmind's AlphaZero chess engine...…☆23Dec 28, 2020Updated 5 years ago
- Equilibrium Verification Environment (EVE) is a formal verification tool for the automated analysis of temporal equilibrium properties of…☆21Aug 31, 2026Updated 3 weeks ago
- Integrating Event-based Dynamic Vision Sensors with Sparse Hyperdimensional Computing☆13Jul 9, 2020Updated 6 years ago
- Package software with ease 📦 Versatile deb, rpm and apk packager fueled by PKGBUILD specfiles and golang☆13Mar 4, 2024Updated 2 years ago
- OpenExSys_CoherentCache a directory-based MESI protocol coherent cache IP.☆26Mar 25, 2025Updated last year
- This is a CNN based model which aims to automatically classify the ECG signals of a normal patient vs. a patient with AF and has been tra…☆52Mar 21, 2021Updated 5 years ago
- ☆18Nov 19, 2023Updated 2 years ago
- ☆18Jul 12, 2024Updated 2 years ago
- Logic Synthesis System from UC Berkeley (Unofficial Distribution)☆15Jun 4, 2019Updated 7 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- Express DLA implementation for FPGA, revised based on NVDLA.☆11Oct 17, 2019Updated 6 years ago
- Vietnamese ID information detection☆19Jun 24, 2022Updated 4 years ago
- Hardware Formal Verification☆18Aug 10, 2020Updated 6 years ago
- ☆15Jul 25, 2024Updated 2 years ago
- ☆18Jul 11, 2021Updated 5 years ago
- BTOR2 MLIR project☆26Jan 17, 2024Updated 2 years ago
- ☆19Dec 21, 2020Updated 5 years ago