Alternatives and similar repositories for myblaze:

Users that are interested in myblaze are comparing it to the libraries listed below

• andrecp / myhdl_simple_uart
  A very simple UART implementation in MyHDL
  ☆17Updated 10 years ago
• udara28 / SDRAM_Controller
  Implementation of a SDRAM controller in MyHDL (http://www.myhdl.org/)
  ☆20Updated 9 years ago
• gtjennings1 / UPDuino-LH154Q01-Display
  Design to connect Lattice Ultraplus FPGA to LH154Q01 Display
  ☆28Updated 6 years ago
• mattvenn / understanding-tinyfpga-bootloader
  understanding the tinyfpga bootloader
  ☆24Updated 6 years ago
• devbisme / myhdlpeek
  Monitor and display signal waveforms from your MyHDL/nMigen digital design in a Jupyter notebook.
  ☆40Updated last year
• daveshah1 / ulx3s
  ☆10Updated 6 years ago
• YosysHQ / yosys-plugins
  Yosys Plugins
  ☆21Updated 5 years ago
• cfelton / gizflo
  that FPGA flow
  ☆9Updated 9 years ago
• mattvenn / crap-o-scope
  crap-o-scope scope implementation for icestick
  ☆20Updated 6 years ago
• stacksmith / fpgasm
  FPGA assembler! Create bare-metal FPGA designs without Verilog or VHDL (Not to self: use Lisp next time)
  ☆53Updated 3 years ago
• pbing / USB
  FPGA USB 1.1 Low-Speed Implementation
  ☆34Updated 6 years ago
• SubProto / icestick-vga-test
  Test of ICEstick PLL usage with Yosys/Arachne-PNR/Icetools
  ☆21Updated 8 years ago
• www-asics-ws / usb1_device
  USB 1.1 Device IP Core
  ☆20Updated 7 years ago
• enjoy-digital / liteiclink
  Small footprint and configurable Inter-Chip communication cores
  ☆56Updated last month
• blackmesalabs / MesaBusProtocol
  Flexible Byte transport protocol for bus bridging CPUs to FPGAs over UART,SPI,SERDES physical interfaces
  ☆32Updated 3 months ago
• cfelton / minnesota
  A collection of HDL cores written in MyHDL.
  ☆12Updated 9 years ago
• mmicko / cross-fpga
  Cross compile FPGA tools
  ☆22Updated 4 years ago
• CospanDesign / nysa
  FPGA Development toolset
  ☆20Updated 7 years ago
• ZipCPU / fftdemo
  A demonstration showing how several components can be compsed to build a simulated spectrogram
  ☆42Updated 11 months ago
• lawrie / tiny_usb_examples
  Using the TinyFPGA BX USB code in user designs
  ☆49Updated 6 years ago
• enjoy-digital / litejesd204b
  Small footprint and configurable JESD204B core
  ☆41Updated 2 months ago
• whitequark / icefloorplan
  iCE40 floorplan viewer
  ☆24Updated 6 years ago
• lawrie / tiny_ram_soc
  Picorv32 SoC that uses only BRAM, not flash memory
  ☆12Updated 6 years ago
• mcci-catena / catena-riscv32-fpga
  RISC-V 32-bit core for MCCI Catena 4710
  ☆10Updated 5 years ago
• daveshah1 / flow-examples
  Misc open FPGA flow examples
  ☆8Updated 5 years ago
• HarmonInstruments / verilog
  ☆20Updated 2 years ago
• gregdavill / litex-hyperram
  Standard HyperRAM core for ECP5 written in Litex/Migen
  ☆14Updated 5 years ago
• barawn / xvcd-anita
  XVCD implementation for ANITA. Note that "ftdi_xvc_core.c" is a generic libftdi-based MPSSE XVC handler, and is awesome.
  ☆18Updated 4 years ago
• stevenbell / csirx
  Open-source CSI-2 receiver for Xilinx UltraScale parts
  ☆35Updated 5 years ago
• Paebbels / PicoBlaze-Library
  The PicoBlaze-Library offers several PicoBlaze devices and code routines to extend a common PicoBlaze environment to a little System on a…
  ☆35Updated 4 years ago