wware / myblazeView external linksLinks
MyBlaze is a synthesizable clone of the MicroBlaze Soft Processor written in MyHDL (http://www.myhdl.org). It started as a translation of MB-Lite from VHDL to MyHDL, along with a simple emulator. Its minimal configuration was tested on the Spartan-3E Starter Kit.
☆17May 30, 2013Updated 12 years ago
Alternatives and similar repositories for myblaze
Users that are interested in myblaze are comparing it to the libraries listed below
Sorting:
- A collection of HDL cores written in MyHDL.☆12Oct 28, 2015Updated 10 years ago
- A very simple UART implementation in MyHDL☆17Aug 21, 2014Updated 11 years ago
- open-source electronics prototyping platform☆28Jan 31, 2017Updated 9 years ago
- This is a myhdl test environment for the open-cores jpeg_encoder.☆18Oct 23, 2016Updated 9 years ago
- FPGA code for NeTV2☆15Dec 3, 2018Updated 7 years ago
- Read only mirror of SVN ChibiOS repository. Official forum http://forum.chibios.org Bugtracker http://sourceforge.net/projects/chibios☆16Sep 2, 2019Updated 6 years ago
- ☆16Jan 25, 2026Updated 2 weeks ago
- A pipelined MIPS processor implemented in Python☆24Mar 31, 2016Updated 9 years ago
- Open source library to handle integers of any size in C☆14Apr 11, 2023Updated 2 years ago
- A collection of MyHDL cores and tools for complex digital circuit design☆86Dec 23, 2018Updated 7 years ago
- Finite state transducer library. Minimalistic pure C implementation.☆14Apr 23, 2020Updated 5 years ago
- HDL tools layer for OpenEmbedded☆17Oct 20, 2024Updated last year
- VDMA framebuffer driver for LVDS display☆14Mar 23, 2017Updated 8 years ago
- iCE40 floorplan viewer☆24Jun 23, 2018Updated 7 years ago
- A library for generating Software Defined Radio-intended DSP code for FPGAs that makes use of the MyHDL (www.myhdl.org) Python library. T…☆25Aug 29, 2012Updated 13 years ago
- A MyHDL library of basic design components, e.g. memory, fifo, multiplexor, de-multiplexor, arbiter, etc.☆17Feb 20, 2020Updated 5 years ago
- Monitor and display signal waveforms from your MyHDL/nMigen digital design in a Jupyter notebook.☆40Jan 22, 2026Updated 3 weeks ago
- Using fixed-point arithmetic in a modern FPGA to produce cool sounds by modeling a 1970s-era Moog-like synthesizer.☆22Dec 2, 2018Updated 7 years ago
- Manfred von Thun's Programming Language Joy☆16Jan 27, 2026Updated 2 weeks ago
- GROM-8 CPU☆20Dec 17, 2017Updated 8 years ago
- ☆54Apr 25, 2017Updated 8 years ago
- ☆19Dec 15, 2023Updated 2 years ago
- Stackless Joy☆23Apr 15, 2025Updated 9 months ago
- A RISC-V CPU (Outdated: using priviledge v1.7)☆26Apr 6, 2019Updated 6 years ago
- Enigma in FPGA☆29May 18, 2019Updated 6 years ago
- shdl6800: A 6800 processor written in SpinalHDL☆25Jan 12, 2020Updated 6 years ago
- A Tiny Processor Core☆114Jul 14, 2025Updated 6 months ago
- Open Processor Architecture☆26Apr 7, 2016Updated 9 years ago
- A highly-configurable and compact variant of the ZPU processor core☆36Sep 12, 2015Updated 10 years ago
- ZPUino HDL implementation☆91Aug 6, 2018Updated 7 years ago
- Val Schorre's META-II☆62Sep 8, 2013Updated 12 years ago
- USB Full-Speed/Hi-Speed Device Controller core for FPGA☆33Nov 23, 2020Updated 5 years ago
- Verilog FT245 to AXI stream interface☆29Jun 20, 2018Updated 7 years ago
- Optimized RISC-V FP emulation for 32-bit processors☆36May 26, 2021Updated 4 years ago
- This is mainly a simulation library of xilinx primitives that are verilator compatible.☆34Jul 15, 2024Updated last year
- Type inference algorithms and intuitionistic propositional theorem provers solving type inhabitation problems☆34Feb 2, 2026Updated last week
- FPGA USB 1.1 Low-Speed Implementation☆35Oct 3, 2018Updated 7 years ago
- A Verilog Synthesis Regression Test☆37Jan 19, 2026Updated 3 weeks ago
- Linux kernel driver for the Exar xr21v141x "vizzini" UART☆10Jul 2, 2015Updated 10 years ago