Wren6991 / tt02-whisk-serial-processor
Whisk: 16-bit serial processor for TT02
☆13Updated 5 months ago
Alternatives and similar repositories for tt02-whisk-serial-processor:
Users that are interested in tt02-whisk-serial-processor are comparing it to the libraries listed below
- Hot Reconfiguration Technology demo☆39Updated 2 years ago
- A Just-In-Time Compiler for Verilog from VMware Research☆22Updated 4 years ago
- Experiments with Yosys cxxrtl backend☆48Updated 2 months ago
- An FPGA reverse engineering and documentation project☆41Updated this week
- End-to-end synthesis and P&R toolchain☆78Updated last week
- RISC-V CPU implementation in Amaranth HDL (aka nMigen)☆29Updated 7 months ago
- Iron: selectively turn RISC-V binaries into hardware☆23Updated last year
- Dual-issue RV64IM processor for fun & learning☆59Updated last year
- Industry standard I/O for Amaranth HDL☆28Updated 5 months ago
- Smol 2-stage RISC-V processor in nMigen☆26Updated 3 years ago
- Exploring gate level simulation☆56Updated 2 years ago
- The Critical Path - a rambly FPGA blog☆49Updated 4 years ago
- RFCs for changes to the Amaranth language and standard components☆18Updated 6 months ago
- Example Verilog code for Ulx3s☆40Updated 2 years ago
- System on Chip toolkit for Amaranth HDL☆86Updated 5 months ago
- u[Dark]RISC -- "micro-darkrisc" -- an early 16-bit micro-RISC processor defined before DarkRISCV☆14Updated last year
- ☆64Updated last year
- User-friendly explanation of Yosys options☆112Updated 3 years ago
- 妖刀夢渡☆59Updated 5 years ago
- Next-Generation FPGA Place-and-Route☆10Updated 6 years ago
- J-Core J2/J32 5 stage pipeline CPU core☆51Updated 4 years ago
- Fiber-based SystemVerilog Simulator.☆25Updated 2 years ago
- ARV: Asynchronous RISC-V Go High-level Functional Model☆24Updated 3 years ago
- Reticle evaluation (PLDI 2021)☆12Updated 3 years ago
- Verilator Porcelain☆49Updated last year
- Small footprint and configurable HyperBus core☆11Updated 2 years ago
- Programs for the FOMU, DE10NANO and ULX3S FPGA boards, written in Silice https://github.com/sylefeb/Silice☆35Updated last year
- Small 32-bit RISC-V CPU with a half-width datapath inspired by the 68000☆16Updated last year
- Reusable Verilog 2005 components for FPGA designs☆40Updated last month
- DDR3 controller for nMigen (WIP)☆14Updated last year