Alternatives and similar repositories for robotframework-kicadlibrary

Users that are interested in robotframework-kicadlibrary are comparing it to the libraries listed below

• cr1901 / sentinel
  Another size-optimized RISC-V CPU for your consideration.
  ☆58Updated this week
• GuzTech / misato
  RISC-V Processor written in Amaranth HDL
  ☆37Updated 3 years ago
• ThePerfectComputer / FastWaveBackend
  A Rust VCD parser intended to be the backend of a Waveform Viewer(built using egui) that supports dynamically loaded rust plugins.
  ☆44Updated 5 months ago
• RTimothyEdwards / irsim
  IRSIM switch-level simulator for digital circuits
  ☆34Updated last month
• martin-robert-fink / superBlink
  RISC-V Assembly with a C wrapper
  ☆12Updated 5 years ago
• enjoy-digital / liteiclink
  Small footprint and configurable Inter-Chip communication cores
  ☆58Updated last week
• b224hisl / rioschip
  ☆33Updated 2 years ago
• openXC7 / nextpnr-xilinx
  Experimental flows using nextpnr for Xilinx devices
  ☆48Updated this week
• lethalbit / kicad-pdk-libs
  KiCad symbol library for sky130 and gf180mcu PDKs
  ☆32Updated last year
• amaranth-lang / amaranth-soc
  System on Chip toolkit for Amaranth HDL
  ☆90Updated 7 months ago
• olofk / subservient
  Small SERV-based SoC primarily for OpenMPW tapeout
  ☆42Updated this week
• azonenberg / antikernel-ipcores
  FPGA IP cores for the Antikernel OS, intended to be included as a submodule in SoC integrations
  ☆64Updated last week
• tomverbeure / gdbwave
  GDB server to debug CPU simulation waveform traces
  ☆44Updated 3 years ago
• mmicko / prjtang
  Documenting the Anlogic FPGA bit-stream format.
  ☆88Updated 2 years ago
• m-labs / VexRiscv-verilog
  Using VexRiscv without installing Scala
  ☆38Updated 3 years ago
• meiniKi / FazyRV
  A minimal-area RISC-V core with a scalable data path to 1, 2, 4, or 8 bits and manifold variants.
  ☆93Updated 9 months ago
• amaranth-lang / rtl-debugger
  VS Code based debugger for hardware designs in Amaranth or Verilog
  ☆38Updated 6 months ago
• antmicro / verilator-dynamic-scheduler-examples
  ☆22Updated 3 weeks ago
• bluespec / RISCV_gdbstub
  A gdbstub for connecting GDB to a RISC-V Debug Module
  ☆30Updated 7 months ago
• mole99 / greyhound-ihp
  Greyhound on IHP SG13G2 0.13 μm BiCMOS process
  ☆38Updated 3 weeks ago
• antmicro / embench-tester
  ☆14Updated last year
• Efinix-Inc / xyloni
  This repo is for Efinix Xyloni development board users. It has projects and software to get you started working with the board.
  ☆42Updated 2 years ago
• fossi-foundation / wishbone
  Specification of the Wishbone SoC Interconnect Architecture
  ☆45Updated 3 years ago
• GMM-7550 / gmm7550-hardware
  CologneChip GateMate FPGA Module: GMM-7550
  ☆22Updated this week
• YosysHQ / padring
  A padring generator for ASICs
  ☆25Updated 2 years ago
• siliconcompiler / logiklib
  Library of FPGA architectures
  ☆21Updated 2 months ago
• Wren6991 / libfpga
  Reusable Verilog 2005 components for FPGA designs
  ☆43Updated 3 months ago
• ECP5-PCIe / ECP5-PCIe
  Mirror of https://codeberg.org/ECP5-PCIe/ECP5-PCIe
  ☆97Updated 2 years ago
• wyvernSemi / usbModel
  USB virtual model in C++ for Verilog
  ☆30Updated 7 months ago
• YosysHQ / nerv
  Naive Educational RISC V processor
  ☆83Updated this week