fjcamillo / Neural-Representation-of-Logic-FunctionsLinks
Creating Logic Functions [AND, OR, NOT, XNOR, XOR, NAND, etc] using Neural Network
☆17Updated 5 years ago
Alternatives and similar repositories for Neural-Representation-of-Logic-Functions
Users that are interested in Neural-Representation-of-Logic-Functions are comparing it to the libraries listed below
Sorting:
- Selected problems and their solutions from the book on "Machine Intelligence in Design Automation"☆26Updated 6 years ago
- Convert C files into Verilog☆16Updated 6 years ago
- Simulated Annealing to minimize the wirelength☆8Updated 8 years ago
- Simple SAT solver with CDCL implemented in Python☆16Updated 2 years ago
- Collection of Papers and Trials on Deep Learning to aid EE design☆44Updated 4 years ago
- Java library for parsing and manipulating graph representations of gate-level Verilog netlists☆13Updated 8 years ago
- Polyhedral Compilation tool for High Level Synthesis.☆10Updated 11 years ago
- ☆21Updated 2 years ago
- Part of paper: Massively Parallel Combinational Binary Neural Networks for Edge Processing☆12Updated 5 years ago
- Arithmetic multiplier benchmarks☆11Updated 7 years ago
- Tutorial for integrating PyMTL and Vivado HLS☆18Updated 9 years ago
- Alpha64 R10000 Two-Way Superscalar Processor☆12Updated 6 years ago
- A Python API for the MiniSat and MiniCard constraint solvers.☆21Updated last year
- ☆13Updated 4 years ago
- EDA Analytics Central☆15Updated 2 years ago
- ☆10Updated 5 years ago
- Logic Synthesis System from UC Berkeley (Unofficial Distribution)☆15Updated 6 years ago
- Training a deep FCN network in PyTorch to route circuit layouts☆67Updated 2 years ago
- Verilog projects for simulation and logic synthesis (Icarus Verilog, YOSYS)☆21Updated 4 years ago
- OpenDesign Flow Database☆16Updated 6 years ago
- ASIC Design kit for Skywater 130 for use with mflowgen☆12Updated 2 years ago
- ☆18Updated 11 months ago
- Simplify VLSI (timing, power, noise, correlation, reliability) modeling and analysis with Characterization Description Format☆12Updated 5 years ago
- A tutorial for setting up Symbolic Quick Error Detection (SQED) using the model checker, CoSA, on the Ride Core☆12Updated 6 years ago
- QuteRTL: A RTL Front-End Towards Intelligent Synthesis and Verification☆16Updated 8 years ago
- Macro placement tool for OpenROAD flow☆23Updated 4 years ago
- Pathfinder routing algorithm practice☆14Updated 8 years ago
- Python version of tools to work with AIG formatted files☆12Updated 2 weeks ago
- EDA wiki☆54Updated 2 years ago
- TAPA is a dataflow HLS framework that features fast compilation, expressive programming model and generates high-frequency FPGA accelerat…☆19Updated 9 months ago