spike556 / HuffmanCodeLinks
hardware implement of huffman coding(written in verilog)
☆12Updated 7 years ago
Alternatives and similar repositories for HuffmanCode
Users that are interested in HuffmanCode are comparing it to the libraries listed below
Sorting:
- ☆20Updated 2 years ago
- ☆55Updated 2 years ago
- Base on Synopsys platform using VCS,DC,ICC,PT.☆12Updated 4 years ago
- a hardware design library based on SpinalHDL, especially for stream processing operators on Xilinx FPGAs for Arithmetic, DSP, Communicati…☆62Updated last year
- LCAI-TIHU HW is an AI inference processor which is comprised of RISC-V cpu, nvdla, NoC bus, PCIe module, DDR, SRAM, bootROM, DMA and peri…☆39Updated 2 years ago
- AXI Interconnect☆49Updated 3 years ago
- ☆29Updated 4 years ago
- Source code of the paper "Low-Cost and Programmable CRC Implementation based on FPGA"☆42Updated 4 years ago
- A generic implementation of AMBA AXI4 communication protocol. The design provides a master, a slave and an interconnect with multiple mas…☆38Updated 2 years ago
- General Purpose AXI Direct Memory Access☆51Updated last year
- verification of simple axi-based cache☆18Updated 6 years ago
- RTL code of some arbitration algorithm☆14Updated 5 years ago
- ☆34Updated 6 years ago
- ☆10Updated 4 years ago
- 128KB AXI cache (32-bit in, 256-bit out)☆51Updated 4 years ago
- FFT generator using Chisel☆60Updated 3 years ago
- SDRAM controller with AXI4 interface☆94Updated 5 years ago
- ☆25Updated 4 years ago
- AXI3 Bus Functional Models (Initiator & Target)☆29Updated 2 years ago
- This repository has a list of collaterals needed for ICC2 workshop. It has a modified version of raven_soc which was taped-out by Efables…☆33Updated 5 years ago
- L1 Data, L1 Instruction and L2 Unified Cache Design FOR RV64IMC☆12Updated 2 years ago
- Verilog Code and Logisim simulation of a Weighted Round Robit Arbiter circuit using digital components☆18Updated 7 years ago
- DDR3 SDRAM Memory Controller Design & Synthesis using System Verilog☆31Updated 6 years ago
- The memory model was leveraged from micron.☆22Updated 7 years ago
- Ethernet MAC IP Core for 100G/50G/40G/25G/10Gbps☆43Updated 2 years ago
- Generic FIFO implementation with optional FWFT☆58Updated 5 years ago
- a cyclic redundancy check(one kind of Error Correcting Code) software(MATLAB) and hardware(Verilog HDL) implementation.☆11Updated 5 years ago
- uvm_axi4lite is a uvm package for modeling and verifying AXI4 Lite protocol☆22Updated 4 months ago
- HDL code for a DDR4 memory controller implementing an Open Page Policy and Out of Order execution.☆75Updated 7 years ago
- Prototype-network-on-chip (ProNoC) is an EDA tool that facilitates prototyping of custom heterogeneous NoC-based many-core-SoC (MCSoC).☆57Updated last week