Alternatives and similar repositories for HuffmanCode

Users that are interested in HuffmanCode are comparing it to the libraries listed below

• zebmehring / Processor-Cache
  A Verilog implementation of a processor cache.
  ☆35Updated 8 years ago
• Chainsaw-Team / Chainsaw
  a hardware design library based on SpinalHDL, especially for stream processing operators on Xilinx FPGAs for Arithmetic, DSP, Communicati…
  ☆67Updated 2 years ago
• LCAI-TIHU / HW
  LCAI-TIHU HW is an AI inference processor which is comprised of RISC-V cpu, nvdla, NoC bus, PCIe module, DDR, SRAM, bootROM, DMA and peri…
  ☆44Updated 3 years ago
• ljgibbslf / basic_cache_core
  ☆31Updated 5 years ago
• aignacio / axi_dma
  General Purpose AXI Direct Memory Access
  ☆62Updated last year
• abdelrhman-oun / DDR5_PHY_WriteOperation
  ☆70Updated 3 years ago
• WangXuan95 / FPGA-Gzip-compressor
  An FPGA-based GZIP (Deflate algorithm) compressor, which inputs raw data and outputs standard GZIP format (as known as .gz file format). …
  ☆150Updated 2 years ago
• IA-C-Lab-Fudan / Chisel-FFT-generator
  FFT generator using Chisel
  ☆63Updated 4 years ago
• whutddk / RiftCore
  RiftCore is a 9-stage, single-issue, out-of-order 64-bits RISC-V Core, which supports RV64IMC and 3-level Cache System
  ☆44Updated 3 years ago
• crypt-xie / XCryptCore
  Implementation of cryptographic algorithm with verilog hdl(such as des,aes,sha,rsa,ecc etc.)
  ☆42Updated 6 years ago
• rajshadow / 4-way-set-associative-cache-verilog
  Verilog implementation of a 4-way Set associative cache with a write buffer (write) policy and FIFO replacement policy
  ☆41Updated 9 years ago
• hizbi-github / AXI4_Master_Interconnect_Slave
  A generic implementation of AMBA AXI4 communication protocol. The design provides a master, a slave and an interconnect with multiple mas…
  ☆43Updated 3 years ago
• olofk / fifo
  Generic FIFO implementation with optional FWFT
  ☆61Updated 5 years ago
• atfox272 / AXI4-Interconnect
  RTL code for AXI4 Interconnect (Verilog). Supports weighted round-robin arbitration, n-channel master, 4Kb splitting, reorder transaction…
  ☆23Updated 10 months ago
• FPGA-Networking / Low-Cost-and-Programmable-CRC
  Source code of the paper "Low-Cost and Programmable CRC Implementation based on FPGA"
  ☆43Updated 5 years ago
• bakhshalipour / NoC-Verilog
  A verilog implementation for Network-on-Chip
  ☆81Updated 8 years ago
• brown9804 / PCIe-Physical-Layer
  Implementation of the PCIe physical layer
  ☆60Updated 6 months ago
• ehao222 / ASIC-design-example-RISC-CPU
  Base on Synopsys platform using VCS,DC,ICC,PT.
  ☆12Updated 4 years ago
• mahmutefil / AXI2APB-Bridge-Design-and-Verification
  In this repository, the RTL design and verification of the axi2apb bridge communication protocol are realized. In this system, the prefer…
  ☆20Updated 3 years ago
• ultraembedded / core_sdram_axi4
  SDRAM controller with AXI4 interface
  ☆100Updated 6 years ago
• lizhirui / AXI-SDCard-High-Speed-Controller
  A SDCard Controller Based AXI4 Bus with SDIO 4-wire 50MHz Mode(Max Rate 23MB/s)
  ☆126Updated 3 years ago
• freecores / round_robin_arbiter
  round robin arbiter
  ☆77Updated 11 years ago
• kuladeepsaireddy / OpenNoc
  ☆40Updated 6 years ago
• ben-marshall / croyde-riscv
  A barebones 64-bit RISC-V micro-controller class CPU, implementing the I(nteger), M(ul/div), C(ompressed) and K(ryptography) extensions.
  ☆48Updated 4 years ago
• lizhirui / DreamCore
  ☆64Updated 3 years ago
• stillwater-sc / RISC-V-TensorCore
  Transactional Verilog design and Verilator Testbench for a RISC-V TensorCore Vector co-processor for reproducible linear algebra
  ☆62Updated 4 years ago
• raymondrc / FPGA_SM4
  FPGA implementation of Chinese SM4 encryption algorithm.
  ☆56Updated 7 years ago
• pulp-platform / fpu
  ☆58Updated 6 years ago
• airin711 / Verilog-caches
  Various caches written in Verilog-HDL
  ☆127Updated 10 years ago
• sifferman / labs-with-cva6
  Advanced Architecture Labs with CVA6
  ☆76Updated 2 years ago