spike556 / HuffmanCodeLinks
hardware implement of huffman coding(written in verilog)
☆12Updated 7 years ago
Alternatives and similar repositories for HuffmanCode
Users that are interested in HuffmanCode are comparing it to the libraries listed below
Sorting:
- ☆28Updated 4 years ago
- Source code of the paper "Low-Cost and Programmable CRC Implementation based on FPGA"☆42Updated 4 years ago
- Verilog Code and Logisim simulation of a Weighted Round Robit Arbiter circuit using digital components☆18Updated 7 years ago
- a hardware design library based on SpinalHDL, especially for stream processing operators on Xilinx FPGAs for Arithmetic, DSP, Communicati…☆62Updated last year
- Implementation of the PCIe physical layer☆40Updated 3 weeks ago
- verification of simple axi-based cache☆18Updated 6 years ago
- LCAI-TIHU HW is an AI inference processor which is comprised of RISC-V cpu, nvdla, NoC bus, PCIe module, DDR, SRAM, bootROM, DMA and peri…☆37Updated 2 years ago
- A Verilog implementation of a processor cache.☆25Updated 7 years ago
- ☆20Updated 2 years ago
- General Purpose AXI Direct Memory Access☆50Updated last year
- commit rtl and build cosim env☆15Updated last year
- Ethernet MAC IP Core for 100G/50G/40G/25G/10Gbps☆44Updated 2 years ago
- DDR3 SDRAM Memory Controller Design & Synthesis using System Verilog☆31Updated 6 years ago
- Implementation of cryptographic algorithm with verilog hdl(such as des,aes,sha,rsa,ecc etc.)☆38Updated 5 years ago
- ☆33Updated 6 years ago
- FFT generator using Chisel☆59Updated 3 years ago
- The controller is a Verilog implementation through a state machine structure per Micro datasheet specifications, and connected to a prede…☆22Updated 6 years ago
- Verilog Code for a JPEG Decoder☆34Updated 7 years ago
- The memory model was leveraged from micron.☆22Updated 7 years ago
- Generic AXI to AHB bridge☆17Updated 10 years ago
- AXI4 and AXI4-Lite interface definitions☆94Updated 4 years ago
- Verilog cache implementation of 4-way FIFO 16k Cache☆19Updated 12 years ago
- SoC Based on ARM Cortex-M3☆32Updated 3 weeks ago
- ☆52Updated 2 years ago
- Translated SpinalHDL-Doc(v1.7.2) into Chinese☆48Updated last year
- Generic FIFO implementation with optional FWFT☆57Updated 5 years ago
- Xilinx AXI VIP example of use☆40Updated 4 years ago
- A generic implementation of AMBA AXI4 communication protocol. The design provides a master, a slave and an interconnect with multiple mas…☆38Updated 2 years ago
- Verilog implementation of a 4-way Set associative cache with a write buffer (write) policy and FIFO replacement policy☆41Updated 8 years ago
- A verilog implementation for Network-on-Chip☆73Updated 7 years ago