spike556 / HuffmanCodeLinks
hardware implement of huffman coding(written in verilog)
☆14Updated 8 years ago
Alternatives and similar repositories for HuffmanCode
Users that are interested in HuffmanCode are comparing it to the libraries listed below
Sorting:
- LCAI-TIHU HW is an AI inference processor which is comprised of RISC-V cpu, nvdla, NoC bus, PCIe module, DDR, SRAM, bootROM, DMA and peri…☆44Updated 2 years ago
- An FPGA-based GZIP (Deflate algorithm) compressor, which inputs raw data and outputs standard GZIP format (as known as .gz file format). …☆146Updated 2 years ago
- a hardware design library based on SpinalHDL, especially for stream processing operators on Xilinx FPGAs for Arithmetic, DSP, Communicati…☆67Updated last year
- General Purpose AXI Direct Memory Access☆61Updated last year
- Implementation of the PCIe physical layer☆59Updated 5 months ago
- A SDCard Controller Based AXI4 Bus with SDIO 4-wire 50MHz Mode(Max Rate 23MB/s)☆126Updated 3 years ago
- ☆66Updated 3 years ago
- A Verilog implementation of a processor cache.☆34Updated 7 years ago
- SDRAM controller with AXI4 interface☆98Updated 6 years ago
- Generic FIFO implementation with optional FWFT☆60Updated 5 years ago
- DDR3 SDRAM Memory Controller Design & Synthesis using System Verilog☆31Updated 7 years ago
- A verilog implementation for Network-on-Chip☆78Updated 7 years ago
- HDL code for a DDR4 memory controller implementing an Open Page Policy and Out of Order execution.☆84Updated 7 years ago
- ☆69Updated 4 years ago
- Dadda multiplier(8*8, 16*16, 32*32) in Verilog HDL.☆37Updated last year
- Source code of the paper "Low-Cost and Programmable CRC Implementation based on FPGA"☆43Updated 4 years ago
- Translated SpinalHDL-Doc(v1.7.2) into Chinese☆51Updated 2 years ago
- RTL code for AXI4 Interconnect (Verilog). Supports weighted round-robin arbitration, n-channel master, 4Kb splitting, reorder transaction…☆19Updated 9 months ago
- ☆31Updated 5 years ago
- Implementation of cryptographic algorithm with verilog hdl(such as des,aes,sha,rsa,ecc etc.)☆41Updated 6 years ago
- FFT generator using Chisel☆62Updated 4 years ago
- ☆57Updated 6 years ago
- Verilog Code and Logisim simulation of a Weighted Round Robit Arbiter circuit using digital components☆20Updated 7 years ago
- In this repository, the RTL design and verification of the axi2apb bridge communication protocol are realized. In this system, the prefer…☆18Updated 3 years ago
- A generic implementation of AMBA AXI4 communication protocol. The design provides a master, a slave and an interconnect with multiple mas…☆42Updated 3 years ago
- AXI4 and AXI4-Lite interface definitions☆97Updated 5 years ago
- ☆64Updated 3 years ago
- ☆39Updated 6 years ago
- AXI Interconnect☆54Updated 4 years ago
- Linux-capable superscalar out-of-order RISC core (with Cache& MMU) and SoC, having been verified on Xilinx Kintex-7 FPGA.☆55Updated last year