Alternatives and similar repositories for OpenMIPS

Users that are interested in OpenMIPS are comparing it to the libraries listed below

• whutddk / Rift2Core
  Based on Chisel3, Rift2Core is a 9-stage, out-of-order, 64-bits RISC-V Core, which supports RV64GC.
  ☆37Updated last year
• lingscale / cc01
  ☆31Updated 2 months ago
• michaelliao / learn-verilog
  Learn Verilog
  ☆35Updated 3 weeks ago
• baochuquan / RISCV-MMU
  ☆14Updated 7 years ago
• zhouqinghua / zqh_riscv
  zqh_riscv is an open source SOC system based on riscv core and tilelink NOC bus. coding with PHGL language(python DSL language). this pro…
  ☆37Updated 3 years ago
• cnrv / clone-helpers
  Helper scripts used to clone RISC-V related git repos inside China.
  ☆15Updated 4 years ago
• RV-AT / PVS32_SoC
  Pan's 1st Gen RISC-V SoC, contains a 12T multicycle RISC-V32ia core, with an EMIF-like simple bus
  ☆16Updated 4 years ago
• Nuclei-Software / nuclei-board-labs
  Nuclei Board Labs
  ☆59Updated last year
• zhangly / azpr_cpu
  用Altera FPGA芯片自制CPU
  ☆41Updated 10 years ago
• JianmingS / MIPS-architecture-CPU-design-based-on-FPGA
  基于FPGA的MIPS架构的CPU设计
  ☆29Updated 9 years ago
• sunyata000 / AMY_MCU
  A MCU implementation based PODES-M0O
  ☆18Updated 5 years ago
• CherrySprings / CherrySprings
  ☆18Updated 2 years ago
• risclite / ARM9-compatible-soft-CPU-core
  This ARMv4-compatible CPU core is written in synthesiable verilog.It could launch uCLinux and Linux in MODELSIM. It has high Dhrystone be…
  ☆82Updated 4 years ago
• amichai-bd / riscv-multi-core-lotr
  RISCV core RV32I/E.4 threads in a ring architecture
  ☆32Updated last year
• wuhanstudio / picorv32_tang
  A 32-bit RISC-V SoC on FPGA that supports RT-Thread.
  ☆28Updated last year
• enjoy-digital / litex_verilog_axi_test
  Integration test of Verilog AXI modules (https://github.com/alexforencich/verilog-axi) with LiteX.
  ☆16Updated 2 years ago
• oscc-ip / sdram
  An open source SDR SDRAM controller based on the AXI4 bus and verified by FPGA and tapeout. It can support memory particles of different …
  ☆17Updated last week
• antmicro / openssd-nvme
  ☆20Updated 4 years ago
• nju-mips / noop-lo
  A simple OoO processor developed by njuallen and wierton, it won 2nd prize in LoongsonCup18.
  ☆28Updated 5 years ago
• AlSaqr-platform / he-soc
  ☆31Updated this week
• NOP-Processor / NOP-SoC
  System-on-chip design for NOP in NSCSCC 2023.
  ☆10Updated last year
• cassuto / nano-cpu32k
  Linux-capable superscalar out-of-order RISC core (with Cache& MMU) and SoC, having been verified on Xilinx Kintex-7 FPGA.
  ☆54Updated 9 months ago
• microdynamics-cpu / tree-core-cpu
  A series of RISC-V soft core processor written from scratch. Now, we're using all open-source toolchain (chisel, mill, verilator, NEMU, …
  ☆40Updated last year
• giuseppedongiovanni / nvme_comp_storage
  Computational Storage Device based on the open source project OpenSSD.
  ☆23Updated 4 years ago
• chipsalliance / chisel-interface
  The 'missing header' for Chisel
  ☆20Updated last month
• redpanda3 / chisel-book
  Hardware design with Chisel
  ☆32Updated 2 years ago
• cnyangkun / nscscc2018
  nscscc2018
  ☆26Updated 6 years ago
• jaruiz / light52
  Yet another free 8051 FPGA core
  ☆34Updated 6 years ago
• jiegec / rocket-chip-vcu128
  Run Rocket Chip on VCU128
  ☆30Updated 5 months ago
• freecores / usbhostslave
  USB 1.1 Host and Function IP core
  ☆23Updated 10 years ago