Alternatives and similar repositories for OpenMIPS

Users that are interested in OpenMIPS are comparing it to the libraries listed below

• whutddk / Rift2Core
  Based on Chisel3, Rift2Core is a 9-stage, out-of-order, 64-bits RISC-V Core, which supports RV64GC.
  ☆39Updated last year
• lingscale / cc01
  ☆30Updated 9 months ago
• shehanmunasinghe / tinyGPU
  tinyGPU: A Predicated-SIMD processor implementation in SystemVerilog
  ☆54Updated 4 years ago
• redpanda3 / chisel-book
  Hardware design with Chisel
  ☆35Updated 2 years ago
• risclite / ARM9-compatible-soft-CPU-core
  This ARMv4-compatible CPU core is written in synthesiable verilog.It could launch uCLinux and Linux in MODELSIM. It has high Dhrystone be…
  ☆89Updated 5 years ago
• cnrv / clone-helpers
  Helper scripts used to clone RISC-V related git repos inside China.
  ☆16Updated 5 years ago
• AlSaqr-platform / he-soc
  ☆32Updated last week
• baochuquan / RISCV-MMU
  ☆14Updated 8 years ago
• nxbyte / ARM-LEGv8
  Verilog Implementation of an ARM LEGv8 CPU
  ☆111Updated 7 years ago
• ultraembedded / riscv-linux-boot
  Trivial RISC-V Linux binary bootloader
  ☆51Updated 4 years ago
• Nuclei-Software / nuclei-board-labs
  Nuclei Board Labs
  ☆58Updated last year
• AlessandroCilardo / NaplesPU
  The official NaplesPU hardware code repository
  ☆20Updated 6 years ago
• zhouqinghua / zqh_riscv
  zqh_riscv is an open source SOC system based on riscv core and tilelink NOC bus. coding with PHGL language(python DSL language). this pro…
  ☆39Updated 4 years ago
• huxuan0307 / XuanTieC910
  Rewrite XuanTieC910 with chisel3
  ☆12Updated 3 years ago
• mpskex / chisel-npu
  Chisel implementation of Neural Processing Unit for System on the Chip
  ☆25Updated 3 months ago
• cassuto / nano-cpu32k
  Linux-capable superscalar out-of-order RISC core (with Cache& MMU) and SoC, having been verified on Xilinx Kintex-7 FPGA.
  ☆55Updated last year
• gzzyyxh / Quafu
  A small SoC with a pipeline 32-bit RISC-V CPU.
  ☆66Updated 3 years ago
• jerry-jho / pyriscv
  A RISCV Emulator written in Python
  ☆46Updated 2 years ago
• chipsalliance / rocket-tools
  Software tools that support rocket-chip (GNU toolchain, ISA simulator, tests)
  ☆59Updated 2 years ago
• bhunt2 / DDR4Sim
  DDR4 Simulation Project in System Verilog
  ☆43Updated 11 years ago
• Nuclei-Software / nuclei-ai-library
  Nuclei AI Library Optimized For RISC-V Vector
  ☆14Updated 2 months ago
• zhangly / azpr_cpu
  用Altera FPGA芯片自制CPU
  ☆43Updated 11 years ago
• EECS150 / fpga_labs_fa21
  FPGA Labs for EECS 151/251A (Fall 2021)
  ☆10Updated 4 years ago
• oscc-ip / sdram
  An open source SDR SDRAM controller based on the AXI4 bus and verified by FPGA and tapeout. It can support memory particles of different …
  ☆21Updated 7 months ago
• cnyangkun / nscscc2018
  nscscc2018
  ☆27Updated 7 years ago
• himanshu5-prog / vortexGPU
  ☆23Updated 4 years ago
• ksco / chibicc-riscv
  A fork of chibicc ported to RISC-V assembly.
  ☆42Updated 3 years ago
• nju-mips / noop-lo
  A simple OoO processor developed by njuallen and wierton, it won 2nd prize in LoongsonCup18.
  ☆30Updated 5 years ago
• rbarzic / nanorv32
  A small 32-bit implementation of the RISC-V architecture
  ☆32Updated 5 years ago
• ic-lab-duth / DRIM-S
  DUTH RISC-V Superscalar Microprocessor
  ☆32Updated last year