Alternatives and similar repositories for OpenMIPS:

Users that are interested in OpenMIPS are comparing it to the libraries listed below

• lingscale / cc01
  ☆31Updated last year
• whutddk / Rift2Core
  Based on Chisel3, Rift2Core is a 9-stage, out-of-order, 64-bits RISC-V Core, which supports RV64GC.
  ☆34Updated 11 months ago
• cnyangkun / nscscc2018
  nscscc2018
  ☆26Updated 6 years ago
• risclite / ARM9-compatible-soft-CPU-core
  This ARMv4-compatible CPU core is written in synthesiable verilog.It could launch uCLinux and Linux in MODELSIM. It has high Dhrystone be…
  ☆77Updated 4 years ago
• cnrv / RVWC2021-slides
  第一届 RISC-V 中国峰会的幻灯片等资料存放
  ☆37Updated 2 years ago
• microdynamics-cpu / tree-core-cpu
  A series of RISC-V soft core processor written from scratch. Now, we're using all open-source toolchain (chisel, mill, verilator, NEMU, …
  ☆37Updated last year
• cnrv / clone-helpers
  Helper scripts used to clone RISC-V related git repos inside China.
  ☆14Updated 4 years ago
• oscourse-tsinghua / LoongsonCsprj2017-manual
  基于龙芯FPGA开发板的计算机综合系统实验
  ☆25Updated 6 years ago
• TianhuaTao / uCore-SMP
  A Symmetric Multiprocessing OS Kernel over RISC-V
  ☆30Updated 2 years ago
• zhouqinghua / zqh_riscv
  zqh_riscv is an open source SOC system based on riscv core and tilelink NOC bus. coding with PHGL language(python DSL language). this pro…
  ☆34Updated 3 years ago
• baochuquan / RISCV-MMU
  ☆14Updated 7 years ago
• OpenXiangShan / YunSuan
  This repo includes XiangShan's function units
  ☆18Updated this week
• Tang-Haojin / YuQuan
  A RISC-V core running Debian (and a LoongArch core running Linux).
  ☆22Updated 10 months ago
• AlSaqr-platform / he-soc
  ☆32Updated this week
• CherrySprings / CherrySprings
  ☆17Updated last year
• oscourse-tsinghua / cpu-testcase
  Test cases for MIPS CPU implementation
  ☆12Updated 5 years ago
• trivialmips / TrivialMIPS
  MIPS32 CPU implemented in SystemVerilog, with superscalar and FPU support
  ☆105Updated 5 years ago
• gzzyyxh / Quafu
  A small SoC with a pipeline 32-bit RISC-V CPU.
  ☆62Updated 2 years ago
• meow-chip / MeowV64
  A superscalar RISC-V CPU with out-of-order execution and multi-core support
  ☆56Updated 2 years ago
• OpenXiangShan / nexus-am
  ☆32Updated this week
• shehanmunasinghe / tinyGPU
  tinyGPU: A Predicated-SIMD processor implementation in SystemVerilog
  ☆42Updated 3 years ago
• YanB25 / Tomasulo
  An out-of-order execution algorithm for pipeline CPU, implemented by verilog
  ☆36Updated 6 years ago
• chipsalliance / chisel-interface
  The 'missing header' for Chisel
  ☆18Updated 3 months ago
• RickyTino / MangoMIPS32
  A softcore microprocessor of MIPS32 architecture.
  ☆39Updated 6 months ago
• sequencer / arithmetic
  ☆32Updated 3 months ago
• jiegec / fpu-wrappers
  Wrappers for open source FPU hardware implementations.
  ☆30Updated 9 months ago
• huxuan0307 / XuanTieC910
  Rewrite XuanTieC910 with chisel3
  ☆11Updated 2 years ago
• RV-AT / PVS32_SoC
  Pan's 1st Gen RISC-V SoC, contains a 12T multicycle RISC-V32ia core, with an EMIF-like simple bus
  ☆15Updated 4 years ago
• Nuclei-Software / nuclei-board-labs
  Nuclei Board Labs
  ☆54Updated last year