DeamonYang / FPGA_SDRLinks
软件无线电,使用FPGA进行正交解调。
☆22Updated 6 years ago
Alternatives and similar repositories for FPGA_SDR
Users that are interested in FPGA_SDR are comparing it to the libraries listed below
Sorting:
- FPGA和USB3.0桥片实现USB3.0通信☆68Updated 3 years ago
- Xilinx FPGA, ADC344X, AD9252, 14x 12x Serdes, LVDS☆50Updated 2 years ago
- FPGA 百兆以太网☆12Updated 6 years ago
- FPGA Technology Exchange Group相关文件管理☆45Updated 3 months ago
- 基于USB2.0 的数据采集卡☆19Updated 6 years ago
- Delta-sigma ADC,PDM audio FPGA Implementation☆71Updated 3 years ago
- The Design and Implementation of a Pulse Compression Filter on an FPGA.☆30Updated 3 years ago
- minimal code to access ps DDR from PL☆20Updated 5 years ago
- MMC小组开发的一个基于Cortex-M0的ARM处理器核的无线SOC设计☆22Updated 2 years ago
- 这是使用FPGA开发CMOS的两个真实项目,之前的fpga_design仅是一个未完善的版本,同时也删除了一些与项目无关的东西☆35Updated 7 years ago
- AD7606 driver verilog☆43Updated 6 years ago
- ☆28Updated 4 years ago
- 这是我所开发的两个项目,包括ov5640-ddr3-usb2.0高速图像采集系统以及NOIP1SN1300A-ddr3-sdhc高速地表图像采集及存储系统☆92Updated 7 years ago
- 基于FPGA的FFT☆19Updated 6 years ago
- A dual-camera based on OminiVison 5460 for GoWin GW2A-55K Combat Board☆33Updated 3 years ago
- 基于arm cortex-m0内核的xillinx fpga sopc工程项目☆13Updated 6 years ago
- It is SATA 3 host controller. Using this you can read write to sata3 sdd/hdd from your fpga logic with simple memory like interface.☆72Updated last year
- FPGA 同步FIFO与异步FIFO☆31Updated 6 years ago
- 本信号处理板主要由FPGA芯片和CYUSB3.0 芯片组成,其中FPGA模块主要完成与相关外设的交互,CYUSB3.0主要完成协议数据的传输。 2.2.1 FPGA模块 处理流程: 1. 链路初始化: 在上位机完成USB固件的下载,并读取…☆28Updated 9 years ago
- Gigabit Ethernet UDP communication driver☆77Updated 5 years ago
- An FPGA-based HDMI display controller. 基于FPGA的HDMI显示控制器☆57Updated last year
- Verilog实现OFDM基带☆44Updated 9 years ago
- Test SRIO connection between FPGA (Kintex-7) and DSP (C6678)☆17Updated 7 years ago
- ⚙️ 基于 Zynq-7 全可编程 SoC 的设计☆35Updated 3 years ago
- Implementation of JESD204B Transport Layer & part of Data Link Layer☆37Updated 4 years ago
- Interfacing ZYNQ SoC device with ADC, Transferring data through DMA and LwIP☆48Updated 4 years ago
- USB2.0 Verilog☆17Updated 6 years ago
- ☆16Updated 3 years ago
- This is use FPGA of Xilinx ZYNQ-7000 ZC702☆17Updated 8 years ago
- 通过调试ADRV9009和AD9371对jesd204b知识点作进一步学习和总结☆23Updated 5 years ago