Huffman encoder
☆10Sep 8, 2013Updated 12 years ago
Alternatives and similar repositories for Huffman-encoder
Users that are interested in Huffman-encoder are comparing it to the libraries listed below
Sorting:
- Verilog Implementation of Run Length Encoding for RGB Image Compression☆27Jun 28, 2021Updated 4 years ago
- BlockCIrculantRNN (LSTM and GRU) using TensorFlow☆14Oct 30, 2018Updated 7 years ago
- RADIX-4 SRT division☆12Oct 31, 2019Updated 6 years ago
- Atom linter for Verilog/SystemVerilog, using Icarus Verilog, Slang, Verible or Verilator.☆10Jul 12, 2023Updated 2 years ago
- JPEG Compression RTL implementation☆11Aug 19, 2017Updated 8 years ago
- Code needed to reproduce results from my ICLR 2019 paper on fixed-point quantization of the backprop algorithm.☆10Jan 24, 2019Updated 7 years ago
- Notes from CodeHelp OS Series☆13Apr 27, 2022Updated 3 years ago
- ☆10Jun 28, 2019Updated 6 years ago
- The code for an FPGA softcore comparison☆11Jun 21, 2020Updated 5 years ago
- hardware implement of huffman coding(written in verilog)☆14Jul 30, 2017Updated 8 years ago
- Demonstration of connection pool for libpqxx. Port from https://github.com/borisovs/pool to work with libpqxx. Tested on Ubuntu 16.04.☆13Jul 5, 2018Updated 7 years ago
- Linux下C语言实现即时通讯系统☆12Jun 3, 2018Updated 7 years ago
- Model LLM inference on single-core dataflow accelerators☆18Dec 16, 2025Updated 2 months ago
- 电子科技大学示范性微电子学院微嵌课程配套代码☆15Dec 10, 2025Updated 2 months ago
- Long Short-Term Memory Neural Networks trained and tested on the TIMIT Acoustic-Phonetic Continuous Speech Corpus.☆11Aug 27, 2017Updated 8 years ago
- ☆14Oct 22, 2023Updated 2 years ago
- Wishbone SATA Controller☆24Oct 16, 2025Updated 4 months ago
- Module giải mã và đóng gói cho các giao thức IP/TCP+UDP. Viết bằng Verilog. Đề tài thực hiện cho Đồ án thiết kế luận lý.☆13Jan 3, 2022Updated 4 years ago
- unsigned Radix-2 SRT division,基2除法☆16May 12, 2015Updated 10 years ago
- HARV - HArdened Risc-V☆16Mar 10, 2022Updated 3 years ago
- Project where we conceptualized and designed a simple neural network accelerator, loosely based on the Eyeriss architecture, to accelerat…☆11Dec 13, 2019Updated 6 years ago
- scripts to convert model formats with blender☆12Aug 5, 2016Updated 9 years ago
- ☆15Aug 16, 2025Updated 6 months ago
- Universal syntax script for all txt docs, logs and other types☆10Sep 21, 2017Updated 8 years ago
- An attempt to reverse engineer a bitstream made for an AL3-10 FPGA☆16Jan 6, 2023Updated 3 years ago
- Udacity NLP Course☆15Nov 22, 2018Updated 7 years ago
- a collection of DRL-repo in Github☆16Oct 21, 2020Updated 5 years ago
- Projects using the Sipeed Tang Primer FPGA development board☆16Dec 6, 2020Updated 5 years ago
- RiscSoC 是一个芯片集成项目,包含了 Cortex-M0、Cortex-M3、MIPS、RISC-V、4-BIT 等内核的 SoC 集成,部分 SoC 使用的自己设计的内核☆12Apr 26, 2022Updated 3 years ago
- Fine Tuning Model for different NLP task☆15Jan 22, 2023Updated 3 years ago
- Asymmetric Numeral Systems - Tabled ANS, C Implementation☆15Mar 20, 2019Updated 6 years ago
- Custom 64-bit pipelined RISC processor☆18Dec 8, 2025Updated 2 months ago
- UVM Python Verification Agents Library☆15Mar 18, 2021Updated 4 years ago
- Lectures and notes, with my honor code as programming exercise.☆17Apr 2, 2014Updated 11 years ago
- Real-Time Image Processing for ASIC/FGPA☆23Feb 23, 2022Updated 4 years ago
- bwt: An ANSI C implementation of the Burrows-Wheeler transformation (BWT)☆18Sep 20, 2019Updated 6 years ago
- Weekly update for SG2042 ecosystem. RISC-V is inevitable!☆22Jul 11, 2025Updated 7 months ago
- Constrained RAndom Verification Enviroment (CRAVE)☆18Nov 23, 2023Updated 2 years ago
- Littlebuzz微型四轴飞行器遥控器源代码☆12Jan 15, 2017Updated 9 years ago