suraj-srinivas / Huffman-encoderLinks
Huffman encoder
☆10Updated 12 years ago
Alternatives and similar repositories for Huffman-encoder
Users that are interested in Huffman-encoder are comparing it to the libraries listed below
Sorting:
- round robin arbiter☆78Updated 11 years ago
- ☆73Updated 7 years ago
- Altera Advanced Synthesis Cookbook 11.0☆113Updated 2 years ago
- 16-bit Adder Multiplier hardware on Digilent Basys 3☆83Updated 2 years ago
- ☆66Updated 3 years ago
- HDLGen is an HDL generation tool, supporting embedded Perl or Python script, reduce manual work & improve effiency with a few embedded f…☆110Updated 2 years ago
- FFT generator using Chisel☆63Updated 4 years ago
- An AXI4 crossbar implementation in SystemVerilog☆208Updated 5 months ago
- INT8 & FP16 multiplier accumulator (MAC) design with UVM verification completed.☆115Updated 5 years ago
- SystemVerilog modules and classes commonly used for verification☆57Updated last month
- IC implementation of TPU☆147Updated 6 years ago
- ☆40Updated 6 years ago
- HDL code for a DDR4 memory controller implementing an Open Page Policy and Out of Order execution.☆85Updated 7 years ago
- RaveNoC is a configurable HDL NoC (Network-On-Chip) suitable for MPSoCs and different MP applications☆187Updated last year
- This repository contains all the parameters you need to synthesize the AlexNet by using Vivado High Level Synthesis.☆21Updated 7 years ago
- Verilog implementation of Softmax function☆80Updated 3 years ago
- ☆82Updated 11 years ago
- AMBA bus generator including AXI, AHB, and APB☆119Updated 4 years ago
- Generic FIFO implementation with optional FWFT☆61Updated 5 years ago
- EE 260 Winter 2017: Advanced VLSI Design☆67Updated 9 years ago
- ☆70Updated 3 years ago
- Deep Learning Accelerator Based on Eyeriss V2 Architecture with custom RISC-V extended instructions☆206Updated 5 years ago
- Xilinx AXI VIP example of use☆43Updated 4 years ago
- A look ahead, round-robing parametrized arbiter written in Verilog.☆43Updated 5 years ago
- NoC (Network-on-Chip) generator that generates Verilog HDL model of NoC consisting of on-chip routers☆76Updated 6 years ago
- For pre-silicon developers of RISC-V systems, riscv-vip is a SystemVerilog project that helps with pre-si verification and debug☆65Updated 5 years ago
- SystemVerilog Direct Programming Interface (DPI) Tutorial☆76Updated 5 years ago
- Convolution Neural Network of vgg19 model in verilog☆49Updated 8 years ago
- ☆58Updated 6 years ago
- AHB DMA 32 / 64 bits☆59Updated 11 years ago