A-suozhang / Verilog_Uart_With_Fifo
Implemented The UART with FIFO
☆14Updated 5 years ago
Alternatives and similar repositories for Verilog_Uart_With_Fifo:
Users that are interested in Verilog_Uart_With_Fifo are comparing it to the libraries listed below
- A small test SoC for various soft-CPUs (Cortex-M0, RISC-V)☆32Updated 5 years ago
- Interface Protocol in Verilog☆49Updated 5 years ago
- A simple Verilog SPI master / slave implementation featuring all 4 modes.☆53Updated 4 years ago
- I present a novel pipelined fast Fourier transform (FFT) architecture which is capable of producing the output sequence in normal order. …☆41Updated last year
- HW JPEG decoder wrapper with AXI-4 DMA☆34Updated 4 years ago
- The RTL desings for the AMBA APB3 Master and Generic Slave ( Memory Interface-able )☆14Updated 2 years ago
- A generic implementation of AMBA AXI4 communication protocol. The design provides a master, a slave and an interconnect with multiple mas…☆38Updated 2 years ago
- Raptor is an SoC Design Template based on Arm Cortex M0 or M3 core.☆19Updated 5 years ago
- A VerilogHDL MCU Core based ARMv6 Cortex-M0☆21Updated 5 years ago
- It is Gate level netlist of MAXVY's MIPI I3C Basic Master Controller IP along with APB interface support.☆16Updated 5 years ago
- UART To SPI☆17Updated 10 years ago
- Final Project for my course in Advanced Verification with SystemVerilog OOP☆21Updated 3 years ago
- FFT implementation using CORDIC algorithm written in Verilog.☆31Updated 6 years ago
- Comprehensive verification suite for the AHB2APB Bridge design, featuring SystemVerilog and UVM-based methodologies. 🌉🚀☆25Updated last year
- DDR3 SDRAM Memory Controller Design & Synthesis using System Verilog☆31Updated 6 years ago
- Implementing Different Adder Structures in Verilog☆65Updated 5 years ago
- This is a project meant to be run on an FPGA that was Implemented in the Verilog HDL using Xilinx ISE design suite.☆22Updated 4 years ago
- AXI Interconnect☆47Updated 3 years ago
- SPI-Flash XIP Interface (Verilog)☆37Updated 3 years ago
- Generic FIFO implementation with optional FWFT☆57Updated 4 years ago
- Verilog module to transmit/receive to/from RGMII compatible ethernet PHY☆23Updated 2 years ago
- Verilog SPI master and slave☆53Updated 9 years ago
- Implementation of ECC on FPGA-Zynq7000 SoC☆17Updated 5 years ago
- ☆17Updated 2 weeks ago
- Generic AXI to AHB bridge☆16Updated 10 years ago
- A set of Wishbone Controlled SPI Flash Controllers☆79Updated 2 years ago
- A 16-point radix-4 FFT chip, including Verilog codes, netlists and layout. Group project.☆61Updated 8 months ago
- DMA Hardware Description with Verilog☆14Updated 5 years ago
- QSPI for SoC☆22Updated 5 years ago
- Designing means to communicate as an SPI master, being a part of AXI interface☆17Updated last year