A-suozhang / Verilog_Uart_With_Fifo
Implemented The UART with FIFO
☆14Updated 5 years ago
Alternatives and similar repositories for Verilog_Uart_With_Fifo
Users that are interested in Verilog_Uart_With_Fifo are comparing it to the libraries listed below
Sorting:
- I present a novel pipelined fast Fourier transform (FFT) architecture which is capable of producing the output sequence in normal order. …☆41Updated last year
- Comprehensive verification suite for the AHB2APB Bridge design, featuring SystemVerilog and UVM-based methodologies. 🌉🚀☆25Updated last year
- The verilog code together with cocotb testbench of BFU unit of a DIF FFT processor☆14Updated 2 years ago
- DMA Hardware Description with Verilog☆14Updated 5 years ago
- Designing means to communicate as an SPI master, being a part of AXI interface☆17Updated last year
- This is a project meant to be run on an FPGA that was Implemented in the Verilog HDL using Xilinx ISE design suite.☆22Updated 5 years ago
- 100DaysofRTL & System Verilog design: basic logic gates, mux, half/full subtractor, Encoder, D flipflop, 8 bit counter, LFSR, Custom Coun…☆34Updated 2 years ago
- Accelerating the AES algorithm on an FPGA and comparing the speedup with both AES and Modified AES algorithms☆27Updated 3 years ago
- Advanced encryption standard (AES) algorithm has been widely deployed in cryptographic applications. This work proposes a low power and h…☆21Updated 4 years ago
- This paper presents design of UART module for serial communication used for short-distance, low speed and exchange of data between comput…☆12Updated 3 years ago
- UART -> AXI Bridge☆61Updated 3 years ago
- Verilog module to transmit/receive to/from RGMII compatible ethernet PHY☆23Updated 2 years ago
- A look ahead, round-robing parametrized arbiter written in Verilog.☆42Updated 4 years ago
- System Verilog using Functional Verification☆10Updated last year
- Generic AXI to AHB bridge☆17Updated 10 years ago
- A VerilogHDL MCU Core based ARMv6 Cortex-M0☆21Updated 5 years ago
- Interface Protocol in Verilog☆49Updated 5 years ago
- The memory model was leveraged from micron.☆22Updated 7 years ago
- Verilog RTL Design☆37Updated 3 years ago
- SoC Based on ARM Cortex-M3☆30Updated last week
- Implementing Different Adder Structures in Verilog☆67Updated 5 years ago
- AXI Interconnect☆49Updated 3 years ago
- Parameterised Asynchronous AHB3-Lite to APB4 Bridge.☆43Updated last year
- ☆19Updated 2 years ago
- The controller is a Verilog implementation through a state machine structure per Micro datasheet specifications, and connected to a prede…☆22Updated 6 years ago
- Hamming ECC Encoder and Decoder to protect memories☆32Updated 3 months ago
- Verilog Design, Simulation & Synthesis of Digital ASIC Projects☆14Updated 2 years ago
- A 32 point radix-2 FFT module written in Verilog☆23Updated 4 years ago
- SystemVerilog examples and projects☆17Updated 6 years ago
- The RTL desings for the AMBA APB3 Master and Generic Slave ( Memory Interface-able )☆14Updated 2 years ago