Alternatives and similar repositories for Verilog_Uart_With_Fifo

Users that are interested in Verilog_Uart_With_Fifo are comparing it to the libraries listed below

• ultraembedded / core_soc
  Basic Peripheral SoC (SPI, GPIO, Timer, UART)
  ☆66Updated 5 years ago
• ultraembedded / core_dbg_bridge
  UART -> AXI Bridge
  ☆63Updated 4 years ago
• ultraembedded / core_sdram_axi4
  SDRAM controller with AXI4 interface
  ☆98Updated 6 years ago
• ultraembedded / core_spiflash
  SPI-Flash XIP Interface (Verilog)
  ☆46Updated 4 years ago
• janschiefer / verilog_spi
  A simple Verilog SPI master / slave implementation featuring all 4 modes.
  ☆69Updated 4 years ago
• halftop / Interface-Protocol-in-Verilog
  Interface Protocol in Verilog
  ☆50Updated 6 years ago
• russdill / bch_verilog
  Verilog based BCH encoder/decoder
  ☆125Updated 3 years ago
• freecores / uart2spi
  UART To SPI
  ☆19Updated 11 years ago
• ultraembedded / core_usb_bridge
  USB -> AXI Debug Bridge
  ☆40Updated 4 years ago
• ultraembedded / fpga_test_soc
  A small test SoC for various soft-CPUs (Cortex-M0, RISC-V)
  ☆34Updated 5 years ago
• WangXuan95 / FPGA-HDMI
  An FPGA-based HDMI display controller. 基于FPGA的HDMI显示控制器
  ☆79Updated last year
• freecores / ethmac
  Ethernet MAC 10/100 Mbps
  ☆84Updated 6 years ago
• damdoy / fpga_image_processing
  IP operations in verilog (simulation and implementation on ice40)
  ☆61Updated 6 years ago
• Lianghao-Yuan / AHB_Bus_Matrix
  ☆38Updated 10 years ago
• alknvl / axis_udp
  This repository contains simple implementation of UDP/IP stack with 64-bit AXI-Stream interface. ICMP and ARP requests are partially supp…
  ☆61Updated 3 years ago
• ahmedshahein / DSP-RTL-Lib
  RTL Verilog library for various DSP modules
  ☆91Updated 3 years ago
• 0xArt / RGMII_Ethernet_Transceiver_Verilog
  Verilog module to transmit/receive to/from RGMII compatible ethernet PHY
  ☆30Updated 2 years ago
• freecores / dma_ahb
  AHB DMA 32 / 64 bits
  ☆56Updated 11 years ago
• Elrori / Delta-sigma-ADC-verilog
  Delta-sigma ADC,PDM audio FPGA Implementation
  ☆73Updated 3 years ago
• siorpaes / BareBonesCortexM0
  Extremely basic CortexM0 SoC based on ARM DesignStart Eval
  ☆27Updated 7 years ago
• DeamonYang / FPGA_SYNC_ASYNC_FIFO
  FPGA 同步FIFO与异步FIFO
  ☆32Updated 6 years ago
• OVGN / OpenHBMC
  Open-source high performance AXI4-based HyperRAM memory controller
  ☆80Updated 3 years ago
• dirjud / Nitro-Parts-lib-SPI
  Verilog SPI master and slave
  ☆61Updated 9 years ago
• sergachev / spi_mem_programmer
  Small (Q)SPI flash memory programmer in Verilog
  ☆65Updated 3 years ago
• ZipCPU / qspiflash
  A set of Wishbone Controlled SPI Flash Controllers
  ☆92Updated 3 years ago
• ultraembedded / core_jpeg_decoder
  HW JPEG decoder wrapper with AXI-4 DMA
  ☆36Updated 5 years ago
• samy-maxvy / MAXVY_MIPI_I3C_Basic_Master_Controller_IP
  It is Gate level netlist of MAXVY's MIPI I3C Basic Master Controller IP along with APB interface support.
  ☆18Updated 5 years ago
• C-Aniruddh / 8bit_sar_adc
  Design and implementation of an 8-bit SAR (Successive Approximation Register) ADC
  ☆26Updated 7 years ago
• adibis / DDR2_Controller
  DDR2 memory controller written in Verilog
  ☆78Updated 13 years ago
• abdelazeem201 / Design-and-ASIC-Implementation-of-32-Point-FFT-Processor
  I present a novel pipelined fast Fourier transform (FFT) architecture which is capable of producing the output sequence in normal order. …
  ☆48Updated last year