This is a SPI Master Module Written in Verilog
☆14Aug 9, 2018Updated 8 years ago
Alternatives and similar repositories for verilog-spi
Users that are interested in verilog-spi are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- MPU6050 interface for fpga☆11May 9, 2020Updated 6 years ago
- Mirror of NeTV FPGA Verilog Code☆15Jan 21, 2012Updated 14 years ago
- Two Verilog SPI module implementations (hard and soft) with advanced options and AXI Full Interface☆22Nov 21, 2017Updated 8 years ago
- hdmi-ts Project☆13Jun 11, 2017Updated 9 years ago
- Implementation of a Serial Peripheral Interface(SPI) using Verilog and testing various modes of the SPI Device☆23Jul 7, 2024Updated 2 years ago
- Virtual machines for every use case on DigitalOcean • AdGet dependable uptime with 99.99% SLA, simple security tools, and predictable monthly pricing with DigitalOcean's virtual machines, called Droplets.
- HDMI + GPU-pipeline + FFT☆15Mar 4, 2016Updated 10 years ago
- 400 nm SiO2 capacitor simulation of interface trap formation with state transitions in Sentaurus TCAD☆17May 26, 2017Updated 9 years ago
- 适用于FPGA——利用串口通信接收幅度频率信息数据帧,控制DA输出相应正弦信号☆10Jul 10, 2019Updated 7 years ago
- An integer queue example used in a blog post at https://www.calhoun.io☆11May 10, 2017Updated 9 years ago
- Implemented The UART with FIFO☆16Jul 4, 2019Updated 7 years ago
- A compact, configurable RISC-V core☆13Jul 31, 2025Updated last year
- Verilog RS232 Enhanced Synch-UART & RS232 Debugger HDL core with PC host RS232 real-time Hex-editor / viewer host utility.☆13Jan 15, 2022Updated 4 years ago
- AllResTool is a tool that allows you to change the resolution on macOS. It allows you to use many possible resolutions, including those t…☆14Jan 24, 2025Updated last year
- ☆13May 21, 2019Updated 7 years ago
- AI Agents on DigitalOcean Gradient AI Platform • AdBuild production-ready AI agents using customizable tools or access multiple LLMs through a single endpoint. Create custom knowledge bases or connect external data.
- We fake out your troubles.☆14Oct 14, 2017Updated 8 years ago
- 基于Verilog实现的串口发送程序,带奇偶校验位。☆12Aug 23, 2019Updated 7 years ago
- This is a SpyDrNet Plugin for a physical design related transformations☆16Updated this week
- A linux'ish build system for System on Chip designs, based on GHDL☆14Dec 14, 2024Updated last year
- SPI Master for FPGA - VHDL and Verilog☆349Aug 22, 2023Updated 3 years ago
- Interface Protocol in Verilog☆52Aug 2, 2019Updated 7 years ago
- OpenMIPS——《自己动手写CPU》处理器部分☆22Mar 4, 2017Updated 9 years ago
- Project and presentation for SpaceX Application☆14Jul 21, 2017Updated 9 years ago
- ☆13May 20, 2018Updated 8 years ago
- Bare Metal GPUs on DigitalOcean Gradient AI • AdPurpose-built for serious AI teams training foundational models, running large-scale inference, and pushing the boundaries of what's possible.
- Oracle Code 2018 Shenzhen☆10Feb 2, 2019Updated 7 years ago
- USB HID keyboard firmware☆10Oct 8, 2021Updated 4 years ago
- ☆13May 4, 2026Updated 4 months ago
- ☆19Mar 6, 2020Updated 6 years ago
- A collection of SPI related cores☆23Nov 12, 2024Updated last year
- I2C Slave☆14Jul 17, 2014Updated 12 years ago
- Attempt to setup a bridge between AHB and I2C by constructing dedicated modules of AHB master , AHB slave , APB master , APB slave, I2C m…☆22Feb 25, 2019Updated 7 years ago
- A SPI Master IP written in verilog which is then used to output characters entered on a keypad to a serial LCD screen☆20Dec 5, 2014Updated 11 years ago
- Verilog code for scanning a four by four matrix keypad.☆14May 26, 2021Updated 5 years ago
- AI Agents on DigitalOcean Gradient AI Platform • AdBuild production-ready AI agents using customizable tools or access multiple LLMs through a single endpoint. Create custom knowledge bases or connect external data.
- 异步FIFO的内部实现☆25Aug 26, 2018Updated 8 years ago
- C++ library for AXI DMA with direct and scatter-gather support☆13Feb 22, 2022Updated 4 years ago
- [Official Repo] WiTUnet: A New U-Shaped Architecture Integrating CNN and Transformer for Improved Feature Alignment and Fuse local and no…☆16Apr 29, 2024Updated 2 years ago
- provide programming exercise automated testing usable by novices☆13Updated this week
- Parsing library for BLIF netlists☆19Nov 1, 2024Updated last year
- ☆22Aug 3, 2026Updated last month
- Controller for i2c EEPROM chip in Verilog for Mojo FPGA board☆27Mar 9, 2016Updated 10 years ago