Alternatives and similar repositories for 8B-10B-Encoder-Decoder

Users that are interested in 8B-10B-Encoder-Decoder are comparing it to the libraries listed below

• Verdvana / AXI4_Interconnect
  AXI总线连接器
  ☆105Updated 5 years ago
• WayneGong / Image_Rotate
  视频旋转（2019FPGA大赛）
  ☆38Updated 5 years ago
• DexWen / FFT_Verilog
  FFT implement by verilog_测试验证已通过
  ☆61Updated 9 years ago
• wudayemen / gen_apb_file
  ☆75Updated 4 years ago
• mgtm98 / pcie5_phy
  PCIE 5.0 Graduation project (Verification Team)
  ☆97Updated 2 years ago
• shun6-6 / Tri_Eth_UDP_pro_stack
  基于FPGA的三速以太网UDP协议栈设计
  ☆35Updated last year
• alknvl / axis_udp
  This repository contains simple implementation of UDP/IP stack with 64-bit AXI-Stream interface. ICMP and ARP requests are partially supp…
  ☆64Updated 3 years ago
• freecores / round_robin_arbiter
  round robin arbiter
  ☆77Updated 11 years ago
• lauchinyuan / Asymmetric_async_FIFO
  asynchronous FIFO that support Non-symmetric aspect ratios(different read and write data widths), First-Word Fall-Through and data counte…
  ☆26Updated 2 years ago
• WangXuan95 / FPGA-Gzip-compressor
  An FPGA-based GZIP (Deflate algorithm) compressor, which inputs raw data and outputs standard GZIP format (as known as .gz file format). …
  ☆150Updated 2 years ago
• freecores / dma_axi
  AXI DMA 32 / 64 bits
  ☆124Updated 11 years ago
• kdurant / axi-ddr3
  学习AXI接口，以及xilinx DDR3 IP使用
  ☆40Updated 8 years ago
• nanamake / r22sdf
  Pipeline FFT Implementation in Verilog HDL
  ☆159Updated 6 years ago
• dadongshangu / async_FIFO
  This asynchrounous FIFO deisgn and UVM verificaiton is one case study of me. The design is based on Cliff Cumming's paper and the UVM is…
  ☆65Updated 2 years ago
• WangXuan95 / FPGA-SATA-HBA
  A SATA host (HBA) core based on Xilinx FPGA with GTH to read/write hard disk. 一个基于Xilinx FPGA中的GTH的SATA host控制器，用来读写硬盘。
  ☆134Updated 2 years ago
• freecores / apbi2c
  APB to I2C
  ☆43Updated 11 years ago
• Aperture-Electronic / SystemVerilog-Bitmap-Library-AXI-Image-VIP
  Bitmap Processing Library & AXI-Stream Video Image VIP
  ☆36Updated 3 years ago
• WangXuan95 / FPGA-FixedPoint
  Verilog implementation of fixed-point numbers, supports custom bit width, arithmetic, converting to float, with single cycle & pipeline v…
  ☆223Updated 2 years ago
• prajwalgekkouga / AHB-to-APB-Bridge
  The AHB to APB bridge is an AHB slave and the only APB master which provides an interface between the highspeed AHB and the low-power APB…
  ☆74Updated 3 years ago
• flyjancy / CortexM0_SoC
  Cortex M0 based SoC
  ☆76Updated 4 years ago
• Lianghao-Yuan / AHB_Bus_Matrix
  ☆38Updated 10 years ago
• WangXuan95 / FPGA-MPEG2-encoder
  An FPGA-based MPEG2 encoder for video compression (1920x1080 120fps). 基于FPGA的MPEG2视频编码器，可实现视频压缩。
  ☆142Updated 2 years ago
• seonskim / verilog_axi-interconnect
  AXI Interconnect
  ☆56Updated 4 years ago
• Nitcloud / Image_sim
  基于FPGA的图像处理模块（出自于crazybingo）（将部分IP换为纯Verilog用于跨平台移植）
  ☆51Updated 5 years ago
• suisuisi / FPGAandImage
  image processing based FPGA
  ☆117Updated 4 years ago
• nelsoncsc / ISP_UVM
  A Framework for Design and Verification of Image Processing Applications using UVM
  ☆117Updated 8 years ago
• ultraembedded / core_sdram_axi4
  SDRAM controller with AXI4 interface
  ☆100Updated 6 years ago
• adki / gen_amba_2021
  AMBA bus generator including AXI4, AXI3, AHB, and APB
  ☆237Updated 2 years ago
• suisuisi / basic_systemverilog
  Must-have verilog systemverilog modules
  ☆37Updated 3 years ago
• ananthbhat94 / DDR4MemoryController
  HDL code for a DDR4 memory controller implementing an Open Page Policy and Out of Order execution.
  ☆85Updated 7 years ago