liyanqing1987 / libView
libView is a GUI tool for library file cell information view and comparison.
☆24Updated last year
Alternatives and similar repositories for libView:
Users that are interested in libView are comparing it to the libraries listed below
- liberty parser (For parsing IC timing lib file)☆55Updated last year
- Educational Design Kit for Synopsys Tools with a set of Characterized Standard Cell Library☆33Updated 3 years ago
- Python-based Verilog Parser (currently Netlist only)☆54Updated 8 years ago
- ideas and eda software for vlsi design☆50Updated this week
- Generate UVM register model from compiled SystemRDL input☆54Updated 7 months ago
- Mirror of Synopsys's Liberty parser library☆21Updated 6 years ago
- A LEF/DEF Utility.☆28Updated 5 years ago
- Python packages providing a library for Verification Stimulus and Coverage☆120Updated last week
- A set of Python based parsers for multiple file format used in IC chip design, including Verilog, SPICE, lib (Synopsys Liberty).☆31Updated 9 years ago
- UVM register utility generation by inputting xls table☆36Updated last year
- IFP (ic flow platform) is an integrated circuit design flow platform, mainly used for IC process specification management and data flow …☆174Updated 4 months ago
- Running Python code in SystemVerilog☆68Updated 9 months ago
- Code to read various RTL simulator wave formats (fsdb, shm, vcd, wlf) into python and apply it as stimuli via cocotb/plain vpi.☆58Updated 3 years ago
- Open Source tool to build liberty files and for Characterizing Standard Cells.☆27Updated 4 years ago
- [WIP] Dockerize Synopsys/Cadence EDA tools☆85Updated 6 years ago
- Python bindings for slang, a library for compiling SystemVerilog☆57Updated 3 months ago
- ☆49Updated 8 years ago
- Introductory course into static timing analysis (STA).☆90Updated this week
- AMC: Asynchronous Memory Compiler☆48Updated 4 years ago
- ☆40Updated 6 years ago
- A complete open-source design-for-testing (DFT) Solution☆148Updated 5 months ago
- SVAUnit is an UVM compliant package that simplify the creation of stimuli/checkers for validating SystemVerilog Assertions (SVA)☆74Updated 4 years ago
- ☆43Updated last year
- Python Tool for UVM Testbench Generation☆52Updated 11 months ago
- HDLGen is an HDL generation tool, supporting embedded Perl or Python script, reduce manual work & improve effiency with a few embedded f…☆96Updated last year
- UVM Auto Generate ; Verify Project Build; Verilog Instance☆34Updated 5 years ago
- SystemVerilog Direct Programming Interface (DPI) Tutorial☆58Updated 4 years ago
- For pre-silicon developers of RISC-V systems, riscv-vip is a SystemVerilog project that helps with pre-si verification and debug☆59Updated 4 years ago
- Library defining all Ethernet packets in SystemVerilog and in SystemC☆36Updated 8 years ago
- Useful UVM extensions☆22Updated 9 months ago