liyanqing1987 / libView
libView is a GUI tool for library file cell information view and comparison.
☆22Updated last year
Related projects ⓘ
Alternatives and complementary repositories for libView
- IFP (ic flow platform) is an integrated circuit design flow platform, mainly used for IC process specification management and data flow …☆162Updated this week
- AMC: Asynchronous Memory Compiler☆46Updated 4 years ago
- Generate UVM register model from compiled SystemRDL input☆51Updated 2 months ago
- ☆100Updated 4 months ago
- ☆42Updated 8 years ago
- This is the repository for the IEEE version of the book☆49Updated 4 years ago
- Python-based Verilog Parser (currently Netlist only)☆52Updated 7 years ago
- This is a tutorial on standard digital design flow☆73Updated 3 years ago
- liberty parser (For parsing IC timing lib file)☆45Updated last year
- Introductory course into static timing analysis (STA).☆66Updated 2 weeks ago
- ☆75Updated last year
- For pre-silicon developers of RISC-V systems, riscv-vip is a SystemVerilog project that helps with pre-si verification and debug☆54Updated 3 years ago
- HDLGen is an HDL generation tool, supporting embedded Perl or Python script, reduce manual work & improve effiency with a few embedded f …☆87Updated last year
- ASIC Design Kit for FreePDK45 + Nangate for use with mflowgen☆151Updated 4 years ago
- Open Source tool to build liberty files and for Characterizing Standard Cells.☆24Updated 3 years ago
- Verilog parser, preprocessor, and related tools for the Verilog-Perl package☆121Updated 10 months ago
- Use ORDT and systemRDL tools to generate C/Verilog header files, register RTL, UVM register models, and docs from compiled SystemRDL.☆66Updated 5 years ago
- A Standalone Structural Verilog Parser☆84Updated 2 years ago
- mflowgen -- A Modular ASIC/FPGA Flow Generator☆233Updated last month
- A generic class library in SystemVerilog☆79Updated 3 years ago
- Code to read various RTL simulator wave formats (fsdb, shm, vcd, wlf) into python and apply it as stimuli via cocotb/plain vpi.☆56Updated 3 years ago
- UVM 1.2 port to Python☆243Updated 8 months ago
- UVM interactive debug library☆32Updated 7 years ago
- amba3 apb/axi vip☆45Updated 9 years ago
- ☆36Updated 7 months ago
- Logic synthesis and ABC based optimization☆46Updated 2 weeks ago
- UVM register utility generation by inputting xls table☆34Updated last year
- ideas and eda software for vlsi design☆47Updated this week
- Mirror of Synopsys's Liberty parser library☆18Updated 6 years ago
- Design of 1024x32 SRAM (32Kbits) using OpenRAM and SKY130 PDKs with operating voltage of 1.8V and access time < 2.5ns☆63Updated 3 years ago