FPGA and Digital ASIC Build System
☆81Mar 5, 2026Updated 3 weeks ago
Alternatives and similar repositories for ruckus
Users that are interested in ruckus are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- A huge VHDL library for FPGA and digital ASIC development☆450Updated this week
- SLAC Python Based Hardware Abstraction & Data Acquisition System☆49Mar 19, 2026Updated last week
- IPbus Builder Tool☆15Mar 5, 2026Updated 3 weeks ago
- IP prototyping in FPGA hardware☆18Aug 28, 2018Updated 7 years ago
- IP-XACT XML binding library☆16Jun 23, 2016Updated 9 years ago
- DigitalOcean Gradient AI Platform • AdBuild production-ready AI agents using customizable tools or access multiple LLMs through a single endpoint. Create custom knowledge bases or connect external data.
- Vivado build system☆70Dec 8, 2025Updated 3 months ago
- experimentation with gnu make for Xilinx Vivado compilation. dependencies can be complicated.☆23Feb 17, 2026Updated last month
- Extensible FPGA control platform☆62Apr 28, 2023Updated 2 years ago
- Firmware that implements a reliable high-performance control link for particle physics electronics, based on the IPbus protocol☆43Mar 5, 2026Updated 3 weeks ago
- Re-coded Xilinx primitives for Verilator use☆52Jun 24, 2025Updated 9 months ago
- Tcl examples repository designed primarily for use with the latest version of the Libero® SoC Design Suite.☆11Jul 18, 2024Updated last year
- A guide to creating custom AXI-lite slave peripherals using the Xilinx Vivado tools☆41Jun 14, 2018Updated 7 years ago
- Software that implements a reliable high-performance control link for particle physics electronics, based on the IPbus protocol☆25Jan 7, 2026Updated 2 months ago
- Example design for the Ethernet FMC using 4 AXI Ethernet Subsystem IP blocks☆72Mar 13, 2026Updated last week
- GPU virtual machines on DigitalOcean Gradient AI • AdGet to production fast with high-performance AMD and NVIDIA GPUs you can spin up in seconds. The definition of operational simplicity.
- HLS implementation of cuckoo hashing. Refer to paper : https://ieeexplore.ieee.org/document/7577355/☆14Dec 4, 2018Updated 7 years ago
- ☆27Updated this week
- Build Customized FPGA Implementations for Vivado☆359Updated this week
- cocotb: Python-based chip (RTL) verification☆2,289Mar 19, 2026Updated last week
- Business Rule Engine Hardware Accelerator☆14Jun 18, 2020Updated 5 years ago
- A parameterizable Vivado HLS project (C/C++) that implements a master and slave AXI-Stream to AXI-Memory-Mapped data mover (AXI-S default…☆16Aug 29, 2018Updated 7 years ago
- Networking Template Library for Vivado HLS☆28Jul 12, 2020Updated 5 years ago
- Documenting the Xilinx 7-series bit-stream format.☆860Jun 5, 2025Updated 9 months ago
- ☆26Feb 11, 2026Updated last month
- Proton VPN Special Offer - Get 70% off • AdSpecial partner offer. Trusted by over 100 million users worldwide. Tested, Approved and Recommended by Experts.
- A simple Vivado (Verilog & VHDL) Continuous Integration tool with seamless integration to Travis-CI☆23Jan 10, 2015Updated 11 years ago
- Xilinx Tcl Store☆372Updated this week
- A PYNQ overlay demonstrating AMD RFSoC Multi-Tile Synchronization (MTS).☆37Jun 22, 2023Updated 2 years ago
- Modular Verilog PCIexpress Interface Components with complete MyHDL Testbench for FPGA deployment☆14Sep 17, 2019Updated 6 years ago
- Xilinx Bitstream Format Library. Easily read .bit files from C programs.☆14Nov 16, 2015Updated 10 years ago
- An RFSoC Frequency Planner developed using Python.☆32May 22, 2023Updated 2 years ago
- A utility for Composing FPGA designs from Peripherals☆187Dec 23, 2024Updated last year
- ☆31Apr 1, 2017Updated 8 years ago
- Various utilities for working with FPGAs☆13Mar 30, 2016Updated 9 years ago
- Simple, predictable pricing with DigitalOcean hosting • AdAlways know what you'll pay with monthly caps and flat pricing. Enterprise-grade infrastructure trusted by 600k+ customers.
- A Python package to use FPGA development tools programmatically.☆146Mar 22, 2025Updated last year
- A git-friendly Vivado wrapper☆247May 21, 2024Updated last year
- ☆18Oct 5, 2020Updated 5 years ago
- Example design for the Ethernet FMC using an FPGA based hardware packet generator/checker to demonstrate maximum throughput☆12Mar 10, 2026Updated 2 weeks ago
- VHDL Bypass descriptor controller for Xilinx DMA IP for PCIe☆18Oct 23, 2019Updated 6 years ago
- hardware library for hwt (= ipcore repo)☆44Dec 23, 2025Updated 3 months ago
- An abstraction library for interfacing EDA tools☆756Updated this week