Alternatives and similar repositories for ruckus:

Users that are interested in ruckus are comparing it to the libraries listed below

• SystemRDL / PeakRDL-regblock
  Generate SystemVerilog RTL that implements a register block from compiled SystemRDL input.
  ☆60Updated 2 weeks ago
• SystemRDL / PeakRDL
  Control and status register code generator toolchain
  ☆119Updated 2 weeks ago
• missinglinkelectronics / fpga-vbs
  Vivado build system
  ☆68Updated 3 months ago
• gsmecher / pyxsi
  Python/C/RTL cosimulation with Xilinx's xsim simulator
  ☆65Updated 6 months ago
• esynr3z / corsair
  Control and Status Register map generator for HDL projects
  ☆113Updated last month
• Toroid-io / vcd2wavedrom
  Python script to transform a VCD file to wavedrom format
  ☆75Updated 2 years ago
• OSVVM / Documentation
  OSVVM Documentation
  ☆33Updated last month
• alexforencich / xfcp
  Extensible FPGA control platform
  ☆59Updated last year
• Xilinx / chipscopy
  ChipScoPy (ChipScope Python API) is an open source Python API to the various ChipScope services provided by the TCF-based (Target Communi…
  ☆53Updated last month
• themperek / cocotb-vivado
  Limited python / cocotb interface to Xilinx/AMD Vivado simulator.
  ☆35Updated 2 months ago
• cocotb / cocotb-bus
  Pre-packaged testbenching tools and reusable bus interfaces for cocotb
  ☆62Updated 5 months ago
• kevinpt / hdlparse
  Simple parser for extracting VHDL documentation
  ☆71Updated 8 months ago
• tmeissner / psl_with_ghdl
  Examples of using PSL for functional and formal verification of VHDL with GHDL (and SymbiYosys)
  ☆66Updated last month
• SystemRDL / PeakRDL-html
  Generate address space documentation HTML from compiled SystemRDL input
  ☆50Updated 6 months ago
• alexforencich / verilog-dsp
  Verilog digital signal processing components
  ☆131Updated 2 years ago
• hdl-registers / hdl-registers
  An open-source HDL register code generator fast enough to run in real time.
  ☆58Updated this week
• paulscherrerinstitute / psi_common
  Common elements for FPGA Design (FIFOs, RAMs, etc.)
  ☆33Updated last month
• MJoergen / formal
  Playing around with Formal Verification of Verilog and VHDL
  ☆55Updated 4 years ago
• antmicro / cocotb-verilator-build
  ☆26Updated last year
• Architech-Silica / Designing-a-Custom-AXI-Slave-Peripheral
  A guide to creating custom AXI-lite slave peripherals using the Xilinx Vivado tools
  ☆40Updated 6 years ago
• fransschreuder / xpm_vhdl
  A translation of the Xilinx XPM library to VHDL for simulation purposes
  ☆53Updated 6 months ago
• hdl-modules / hdl-modules
  A collection of reusable, high-quality, peer-reviewed VHDL building blocks.
  ☆159Updated last week
• airhdl / spi-to-axi-bridge
  An SPI to AXI4-lite bridge for easy interfacing of airhdl register banks with any microcontroller.
  ☆49Updated last year
• OSVVM / OsvvmLibraries
  Start here. Includes all other OSVVM libraries as submodules: Utility, Common, Verification Component, and Script.
  ☆58Updated 2 weeks ago
• suoto / fpga_cores
  ☆33Updated last year
• os-fpga / FOEDAG
  Framework Open EDA Gui
  ☆64Updated 3 months ago
• MikePopoloski / pyslang
  Python bindings for slang, a library for compiling SystemVerilog
  ☆55Updated 2 months ago
• avelure / doxygen-verilog
  Doxygen with verilog support
  ☆37Updated 6 years ago
• fusesoc / fusesoc-cores
  FuseSoC standard core library
  ☆129Updated last month
• kevinpt / symbolator
  HDL symbol generator
  ☆189Updated 2 years ago