strath-sdr / rfsoc_frequency_plannerLinks
An RFSoC Frequency Planner developed using Python.
☆31Updated 2 years ago
Alternatives and similar repositories for rfsoc_frequency_planner
Users that are interested in rfsoc_frequency_planner are comparing it to the libraries listed below
Sorting:
- RFSoC2x2 board repo for PYNQ☆17Updated 3 years ago
- The Strathclyde RFSoC Studio Installer for PYNQ.☆34Updated 2 years ago
- RFSoC Spectrum Analyser Module on PYNQ.☆89Updated last year
- PYNQ example of using the RFSoC as a QPSK transceiver.☆109Updated 2 years ago
- PYNQ example of using the RFSoC as a QPSK/BPSK radio transceiver.☆40Updated 2 years ago
- Demonstration of Automatic Gain Control with PYNQ☆16Updated 3 years ago
- PYNQ example of an OFDM Transmitter and Receiver on RFSoC.☆58Updated 2 years ago
- Python productivity for RFSoC platforms☆85Updated 2 months ago
- RFSoC QSFP Data Offload Design with GNU Radio☆25Updated last year
- A collection of RFSoC introductory notebooks for PYNQ.☆25Updated 4 years ago
- An efficient implementation of the Viterbi decoding algorithm in Verilog☆59Updated last year
- Board repo for the ZCU216 RFSOC☆31Updated 3 years ago
- A PYNQ overlay demonstrating the Xilinx RFSoC SD-FEC☆13Updated 3 years ago
- A PYNQ overlay demonstrating AMD RFSoC Multi-Tile Synchronization (MTS).☆31Updated 2 years ago
- Verilog Forward Error Correction Archive: BOX-Muller for fast AWGN generation, Universal Demapper from BPSK to QAM-512, different Forward…☆80Updated 2 years ago
- ☆19Updated 4 years ago
- FEC Codec IP core library for a some famous codes (BCH, RS, LDPC, Turbo)☆129Updated 2 weeks ago
- Open-sourcing the PYNQ & RFSoC workshop materials☆63Updated 5 years ago
- Companion Jupyter Notebooks for the RFSoC-Book.☆247Updated 2 years ago
- A PYNQ overlay demonstrating Pythonic DSP running on Zynq UltraScale+☆40Updated 3 years ago
- HDL code for a complex multiplier with AXI stream interface☆16Updated 2 years ago
- Common elements for FPGA Design (FIFOs, RAMs, etc.)☆39Updated 10 months ago
- RTL implementation of components for DVB-S2☆130Updated 2 years ago
- HDL code for a complex multiplier with AXI stream Interface☆13Updated 2 years ago
- A collection of phase locked loop (PLL) related projects☆115Updated last year
- Extensible FPGA control platform☆61Updated 2 years ago
- Dual-Mode PSK Transceiver on SDR With FPGA☆50Updated last year
- ☆33Updated 2 years ago
- LBNL RF controls support HDL libraries. Mirroring LBNL's internal Gitlab repository, which is CI enabled☆108Updated this week
- Fixed-point library with bittrue implementations in VHDL (for FPGA) and python (for simulation)☆27Updated last year