strath-sdr / rfsoc_frequency_plannerLinks
An RFSoC Frequency Planner developed using Python.
☆31Updated 2 years ago
Alternatives and similar repositories for rfsoc_frequency_planner
Users that are interested in rfsoc_frequency_planner are comparing it to the libraries listed below
Sorting:
- The Strathclyde RFSoC Studio Installer for PYNQ.☆33Updated 2 years ago
- Demonstration of Automatic Gain Control with PYNQ☆15Updated 3 years ago
- RFSoC2x2 board repo for PYNQ☆17Updated 2 years ago
- Python productivity for RFSoC platforms☆80Updated this week
- PYNQ example of using the RFSoC as a QPSK/BPSK radio transceiver.☆37Updated 2 years ago
- RFSoC Spectrum Analyser Module on PYNQ.☆87Updated last year
- PYNQ example of using the RFSoC as a QPSK transceiver.☆108Updated 2 years ago
- PYNQ example of an OFDM Transmitter and Receiver on RFSoC.☆53Updated 2 years ago
- RFSoC QSFP Data Offload Design with GNU Radio☆24Updated 10 months ago
- A collection of RFSoC introductory notebooks for PYNQ.☆23Updated 3 years ago
- Verilog Forward Error Correction Archive: BOX-Muller for fast AWGN generation, Universal Demapper from BPSK to QAM-512, different Forward…☆76Updated 2 years ago
- A PYNQ overlay demonstrating AMD RFSoC Multi-Tile Synchronization (MTS).☆27Updated 2 years ago
- FEC Codec IP core library for a some famous codes (BCH, RS, LDPC, Turbo)☆121Updated last year
- Board repo for the ZCU216 RFSOC☆30Updated 3 years ago
- An efficient implementation of the Viterbi decoding algorithm in Verilog☆55Updated last year
- ☆19Updated 4 years ago
- Companion Jupyter Notebooks for the RFSoC-Book.☆230Updated 2 years ago
- LBNL RF controls support HDL libraries. Mirroring LBNL's internal Gitlab repository, which is CI enabled☆65Updated last week
- Open-sourcing the PYNQ & RFSoC workshop materials☆63Updated 4 years ago
- A PYNQ overlay demonstrating the Xilinx RFSoC SD-FEC☆13Updated 3 years ago
- A collection of phase locked loop (PLL) related projects☆110Updated last year
- HDL code for a complex multiplier with AXI stream Interface☆13Updated 2 years ago
- A PYNQ overlay demonstrating Pythonic DSP running on Zynq UltraScale+☆40Updated 3 years ago
- RTL implementation of components for DVB-S2☆126Updated 2 years ago
- A High-Throughput Oversampled Polyphase Filter Bank Using Vivado HLS and PYNQ on a RFSoC☆37Updated last year
- HDL code for a complex multiplier with AXI stream interface☆16Updated 2 years ago
- Transfer data over UDP with a Zedboard. This is an example project that transmits and receives data over UDP.☆27Updated 4 years ago
- ☆21Updated last week
- Software control for CASPER FPGAs☆21Updated last month
- A basic Soft(Gate)ware Defined Radio architecture☆94Updated last year