Alternatives and similar repositories for rfsoc_frequency_planner

Users that are interested in rfsoc_frequency_planner are comparing it to the libraries listed below

• strath-sdr / rfsoc_studio
  The Strathclyde RFSoC Studio Installer for PYNQ.
  ☆34Updated 2 years ago
• Xilinx / RFSoC2x2-PYNQ
  RFSoC2x2 board repo for PYNQ
  ☆17Updated 3 years ago
• strath-sdr / pynq_agc
  Demonstration of Automatic Gain Control with PYNQ
  ☆16Updated 3 years ago
• Xilinx / RFSoC-PYNQ
  Python productivity for RFSoC platforms
  ☆84Updated 2 weeks ago
• strath-sdr / rfsoc_qpsk
  PYNQ example of using the RFSoC as a QPSK transceiver.
  ☆108Updated 2 years ago
• strath-sdr / rfsoc_sam
  RFSoC Spectrum Analyser Module on PYNQ.
  ☆87Updated last year
• strath-sdr / rfsoc_radio
  PYNQ example of using the RFSoC as a QPSK/BPSK radio transceiver.
  ☆40Updated 2 years ago
• strath-sdr / rfsoc_ofdm
  PYNQ example of an OFDM Transmitter and Receiver on RFSoC.
  ☆55Updated 2 years ago
• strath-sdr / rfsoc_notebooks
  A collection of RFSoC introductory notebooks for PYNQ.
  ☆24Updated 4 years ago
• strath-sdr / rfsoc_qsfp_offload
  RFSoC QSFP Data Offload Design with GNU Radio
  ☆25Updated 11 months ago
• sarafs1926 / ZCU216-PYNQ
  Board repo for the ZCU216 RFSOC
  ☆30Updated 3 years ago
• Xilinx / SDFEC-PYNQ
  A PYNQ overlay demonstrating the Xilinx RFSoC SD-FEC
  ☆13Updated 3 years ago
• Xilinx / RFSoC-MTS
  A PYNQ overlay demonstrating AMD RFSoC Multi-Tile Synchronization (MTS).
  ☆30Updated 2 years ago
• Lcrypto / FEC-Archive-Verilog
  Verilog Forward Error Correction Archive: BOX-Muller for fast AWGN generation, Universal Demapper from BPSK to QAM-512, different Forward…
  ☆77Updated 2 years ago
• jfoshea / Viterbi-Decoder-in-Verilog
  An efficient implementation of the Viterbi decoding algorithm in Verilog
  ☆58Updated last year
• strath-sdr / RFSoC-Book
  Companion Jupyter Notebooks for the RFSoC-Book.
  ☆239Updated 2 years ago
• JennySmith888 / 100GBE-PYNQ
  ☆19Updated 4 years ago
• Xilinx / PYNQ_RFSOC_Workshop
  Open-sourcing the PYNQ & RFSoC workshop materials
  ☆63Updated 5 years ago
• dshekhalev / FEC
  FEC Codec IP core library for a some famous codes (BCH, RS, LDPC, Turbo)
  ☆124Updated last week
• Xilinx / DSP-PYNQ
  A PYNQ overlay demonstrating Pythonic DSP running on Zynq UltraScale+
  ☆40Updated 3 years ago
• ZipCPU / dpll
  A collection of phase locked loop (PLL) related projects
  ☆112Updated last year
• MazinLab / RFSoC_OPFB
  A High-Throughput Oversampled Polyphase Filter Bank Using Vivado HLS and PYNQ on a RFSoC
  ☆38Updated last year
• OpenResearchInstitute / dvb_fpga
  RTL implementation of components for DVB-S2
  ☆128Updated 2 years ago
• BerkeleyLab / Bedrock
  LBNL RF controls support HDL libraries. Mirroring LBNL's internal Gitlab repository, which is CI enabled
  ☆66Updated this week
• catkira / complex_multiplier
  HDL code for a complex multiplier with AXI stream Interface
  ☆13Updated 2 years ago
• hukenovs / intfftk
  Fully pipelined Integer Scaled / Unscaled Radix-2 Forward/Inverse Fast Fourier Transform (FFT) IP-core for newest Xilinx FPGAs (Source la…
  ☆87Updated 2 years ago
• alexforencich / xfcp
  Extensible FPGA control platform
  ☆61Updated 2 years ago
• Xilinx / Vitis_Model_Composer
  Vitis Model Composer Examples and Tutorials
  ☆108Updated this week
• owocomm-0 / fpga-fft
  A highly optimized streaming FFT core based on Bailey's 4-step large FFT algorithm
  ☆122Updated 4 years ago
• mathworks / HDL-Coder-Self-Guided-Tutorial
  Learn how to deploy an algorithm to an FPGA using MATLAB and Simulink.
  ☆86Updated 10 months ago