Architech-Silica / Designing-a-Custom-AXI-Slave-PeripheralLinks
A guide to creating custom AXI-lite slave peripherals using the Xilinx Vivado tools
☆41Updated 7 years ago
Alternatives and similar repositories for Designing-a-Custom-AXI-Slave-Peripheral
Users that are interested in Designing-a-Custom-AXI-Slave-Peripheral are comparing it to the libraries listed below
Sorting:
- An SPI to AXI4-lite bridge for easy interfacing of airhdl register banks with any microcontroller.☆52Updated 2 years ago
- A guide to creating custom AXI4 masters using the Xilinx Vivado tools and Bus Functional Models☆35Updated 7 years ago
- ☆33Updated 2 years ago
- Python/C/RTL cosimulation with Xilinx's xsim simulator☆76Updated 4 months ago
- Extensible FPGA control platform☆61Updated 2 years ago
- ☆26Updated 2 years ago
- Example design for the Ethernet FMC using 4 AXI Ethernet Subsystem IP blocks☆71Updated 7 months ago
- Collection of all FPGA related PSI libraries in the correct folder strucutre. Each library is included as submodule.☆42Updated 2 months ago
- Repository gathering basic modules for CDC purpose☆56Updated 5 years ago
- FPGA and Digital ASIC Build System☆80Updated 3 weeks ago
- UART models for cocotb☆32Updated 3 months ago
- An open-source HDL register code generator fast enough to run in real time.☆77Updated last week
- A simple DDR3 memory controller☆61Updated 2 years ago
- SDRAM controller for MIPSfpga+ system☆24Updated 5 years ago
- Slides and lab instructions for the mastering MicroBlaze session☆37Updated 3 years ago
- AXI Stream UART (verilog)☆12Updated 6 years ago
- Vivado build system☆69Updated last week
- Documentation with code examples about interfacing VHDL with foreign languages and tools through GHDL☆51Updated this week
- Verilog wishbone components☆124Updated last year
- ☆18Updated 9 years ago
- A collection of phase locked loop (PLL) related projects☆114Updated last year
- Common elements for FPGA Design (FIFOs, RAMs, etc.)☆38Updated 9 months ago
- experimentation with gnu make for Xilinx Vivado compilation. dependencies can be complicated.☆23Updated 2 years ago
- File editor for the Xilinx AXI Traffic Generator IP☆16Updated last year
- Fork of OpenCores jpegencode with Cocotb testbench☆46Updated 10 years ago
- A series of CORDIC related projects☆120Updated last year
- ChipScoPy (ChipScope Python API) is an open source Python API to the various ChipScope services provided by the TCF-based (Target Communi…☆62Updated last week
- ☆76Updated 3 years ago
- SpinalHDL Hardware Math Library☆93Updated last year
- Ethernet interface modules for Cocotb☆71Updated 3 months ago