Viq111 / Vivado-CILinks
A simple Vivado (Verilog & VHDL) Continuous Integration tool with seamless integration to Travis-CI
☆23Updated 11 years ago
Alternatives and similar repositories for Vivado-CI
Users that are interested in Vivado-CI are comparing it to the libraries listed below
Sorting:
- Extensible FPGA control platform☆61Updated 2 years ago
- Fork of OpenCores jpegencode with Cocotb testbench☆46Updated 10 years ago
- ChipScoPy (ChipScope Python API) is an open source Python API to the various ChipScope services provided by the TCF-based (Target Communi…☆64Updated last month
- Python interface to PCIE☆40Updated 7 years ago
- SystemVerilog DPI "TCP/IP Shunt" (System Verilog/SystemC/Python TCP/IP socket library)☆52Updated 6 months ago
- Tutorials, scripts and reference designs for the Intel FPGA partial reconfiguration (PR) design flow☆90Updated 10 months ago
- Facilitates building open source tools for working with hardware description languages (HDLs)☆66Updated 6 years ago
- Open Source PHY v2☆33Updated last year
- A guide to creating custom AXI4 masters using the Xilinx Vivado tools and Bus Functional Models☆35Updated 7 years ago
- Python library for working Standard Delay Format (SDF) Timing Annotation files.☆30Updated last year
- ☆21Updated 9 years ago
- A collection of awesome MyHDL tutorials, projects and third-party tools.☆93Updated 4 years ago
- Generates Makefiles to synthesize, place, and route verilog using Vivado☆97Updated 3 years ago
- Hamming ECC Encoder and Decoder to protect memories☆34Updated last year
- IP-core package generator for AXI4/Avalon☆22Updated 7 years ago
- ☆26Updated this week
- Python script to transform a VCD file to wavedrom format☆84Updated 3 years ago
- A guide to creating custom AXI-lite slave peripherals using the Xilinx Vivado tools☆41Updated 7 years ago
- FPGA and Digital ASIC Build System☆81Updated 3 weeks ago
- Open source 10 Gigabit Ethernet MAC core compatible with Xilinx's non-free 10GMAC☆72Updated 9 years ago
- Dockerfile with Vivado for CI☆63Updated 8 years ago
- Code to read various RTL simulator wave formats (fsdb, shm, vcd, wlf) into python and apply it as stimuli via cocotb/plain vpi.☆63Updated 4 years ago
- This is a circular buffer controller used in FPGA.☆34Updated 10 years ago
- VM-HDL Co-Simulation for Servers with PCIe-Connected FPGAs☆52Updated 5 years ago
- JTAG DPI module for SystemVerilog RTL simulations☆31Updated 10 years ago
- ☆36Updated 5 years ago
- This is the repository for a verilog implementation of a lzrw1 compression core☆19Updated 8 years ago
- OpTiMSoC - A tiled SoC platform with a mesh NoC and OpenRISC CPU cores☆88Updated 4 years ago
- Open source FPGA-based NIC and platform for in-network compute☆67Updated 5 months ago
- ☆26Updated 2 years ago